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FPGA implementation of Canny edge detection by using Vivado HLS

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HLS-canny-edge-detection

FPGA Implementation of Canny edge detection by using Vivado HLS

Feature

  • Protocol of input and output are AXI4-Stream
  • IP core made by this code can run close to 1pix/clock because of pipeline processing
  • You can make other image processing module that are like sequential access based on this code design

Example

C simulation result C simulation result

Reference

Akira Yamawaki, Seiichi Serikawa, “A describing method of an image processing software in C for a high-level synthesis considering a function chaining,” IEICE trans. inf. & syst., vol.E101-D, no.2, February 2018.

License

MIT

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FPGA implementation of Canny edge detection by using Vivado HLS

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