[Feature Request] support "region" comments to allow collapsing blocks of code

[DeflateAwning]

Most languages support collapsing blocks of code by wrapping that block of code in a comment like:

// C example

// region boring variable assignments
int a = 1;
float b = 2;
char somestr = "some string value";
// endregion <optionally repeat the name of the region>

This doesn't appear to be supported in this verilog plugin yet. It's supported in C, Python, Java, C#, etc., so I'd call it pretty standard.

In Verilog, it's reasonably common to generate long code using a scripting language, so it would be helpful to be able to collapse it.

Here is an example test case, in Verilog:

module sample_coefficients(
        input [7:0] index_to_request,
        output [4:0] requested_coefficient
    );

    // 255 coefficients, each 5 bits wide
    reg [255:0] coeffs_const [4:0];
    
    // region assign coeffs_const values
    assign coeffs_const[0] = 5'd0;
    assign coeffs_const[1] = 5'd2;
    assign coeffs_const[2] = 5'd4;
    assign coeffs_const[3] = 5'd0;
    assign coeffs_const[4] = 5'd13;
    assign coeffs_const[5] = 5'd22;
    assign coeffs_const[6] = 5'd0;
    // .. many more assigns, up to 255 index
    // endregion assign coeffs_const values

    assign requested_coefficient = coeffs_const[index_to_request];
endmodule