[BUG] Module instantiation doesn't instantiate parameters

[toTheSky]

Describe the bug
Module instantiation instantiates ports but not parameters.

Environment (please complete the following information):

• OS: Win 11
• VS Code version 1.88.0
• Extension version 1.13.5
• ctags version v6.1.0 x64

Steps to reproduce
Steps to reproduce the behavior:

1. Run Command Palette
2. Type and run "Verilog: Instantiate Module"
3. Select Verilog of SystemVerilog file
4. See error

Log
I don't know where the log is located.

Expected behavior
Parameters should be instantiated too.

Actual behavior
Only ports are instantiated.

Additional context
I tried to add additional arguments to ctags path (ctags.exe --fields-Verilog=+{parameter}) but it does't help.

[AndrewNolte]

This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type 'Module #(, and it support interfaces

[toTheSky]

This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type 'Module #(, and it support interfaces

Thanks. Can it be merged with the main repo?

[AndrewNolte]

This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type 'Module #(, and it support interfaces

Thanks. Can it be merged with the main repo?

I forked off quite a bit to move faster with improvements, it's on the marketplace https://marketplace.visualstudio.com/items?itemName=AndrewNolte.vscode-system-verilog