Dependencies

Steps

Create an SVG file where each circuit node is in an SVG group, and give the group a unique (hopefully meaningful) name.
Create a VCD file (I use GHDL, but Verilog tools should work too) which records the timing behavior of the signals you care about
Create a JSON config file which associates the VCD signal names with the SVG groups
Run the animatetiming.py script

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
LICENSE.txt		LICENSE.txt
Makefile		Makefile
README.md		README.md
andgate.json		andgate.json
andgate.svg		andgate.svg
andgate.vhd		andgate.vhd
animatetiming.py		animatetiming.py
carrylookahead.svg		carrylookahead.svg
config_ripplecarry.json		config_ripplecarry.json
fulladder.svg		fulladder.svg
fulladder.vhd		fulladder.vhd
fulladder_config.json		fulladder_config.json
ripplecarry.svg		ripplecarry.svg
test_carrylookahead.vhd		test_carrylookahead.vhd
test_fulladder.vhd		test_fulladder.vhd
test_ripplecarry.vhd		test_ripplecarry.vhd