Pinned

1. asynchronous_fifo asynchronous_fifo Public

   Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.

   Verilog 23 6

2. memory_verification_using_system_verilog memory_verification_using_system_verilog Public

   In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component

   SystemVerilog 6 1

3. verilog_memeory verilog_memeory Public

   Verilog 2

4. Dual_port_ram Dual_port_ram Public

   dual clock dual port ram using verilog and system verilog

   SystemVerilog 3

5. two-port-switch-test two-port-switch-test Public

   two port switch contaning router

   SystemVerilog 2

6. Uart_tx_main Uart_tx_main Public

   Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directio…

   Verilog 2