透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

An implementation of the popular Tron arcade game on the Altera DE2-115 board for UNLV CpE 302 Synthesis and Verification Using Programmable Devices final.

An implementation of a simple 8-bit microprocessor on an Altera DE2-115 board for UNLV CpE 300L Digital Systems Architecture and Design final project.

Creating a 32-bit single cycle processor using VHDL on Altera Quartus and MIPS assembly commands. Each component was created and emulated using VHDL code. After creating block symbols of each component, the entire processor was connected and compiled for functionality.

4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.

Altera Quartus Project for Fundamentals of Computer Engineering subject

Lab exercises on digital circuit design using Altera Quartus 9.1sp2

A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT