building blocks for accelerating ZK proofs over binary fields
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Updated
May 27, 2024 - C++
building blocks for accelerating ZK proofs over binary fields
The Accelerator Integration Tool (AIT) automatically integrates OmpSs@FPGA accelerators into FPGA designs using different vendor backends
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Innervator: Hardware Acceleration for Artificial Neural Networks in FPGA using VHDL.
GraphBlox: A Vertex Centric Re-Configurable Graph Accelerator Overlay
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
Meus programas que fiz durante o curso de ciencias da computacao
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
Small project to track things with a waterproof sonar sensor
blaze is a Rust library for ZK acceleration on Xilinx FPGAs.
Meta-repository for OmpSs-2@FPGA releases
Zynq-7000 PS side drivers for SLCR Registers.
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository
Re-coded Xilinx primitives for Verilator use
The code allows anyone with the Artix A7 FPGA Board to Blink the On-Board LED for any predefined Frequency.
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.
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