xilinx-vivado
Here are 153 public repositories matching this topic...
FPGA design and implementation of multi-cycle 32-bits pipelined MIPS processor
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Nov 13, 2022 - C
3rd Order Moving Average(FIR) Filter Implementation On FPGA.
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Nov 10, 2023 - Verilog
A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.
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Feb 29, 2024 - VHDL
Implementation of a MIPS processor on a Xilinx Artix-7 FPGA.
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May 19, 2023 - Verilog
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Nov 30, 2020 - Objective-C
Zynq Book Tutorials adapted for the Digilent PYNQ-Z1
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Feb 11, 2023 - Tcl
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
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Apr 27, 2024 - Verilog
A repo for ECE 440 (Digital Systems Engineering) class projects
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Apr 17, 2020 - VHDL
A collection of code from CDA 4240C: Design of Digital System and Lab
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May 26, 2023 - VHDL
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Mar 23, 2023 - C
Design and Implementation of Arithmetic Logic Unit Capable of Calculating Z=1/4(A X B)+1
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Jul 6, 2023 - VHDL
A 4-bit down counter is a digital circuit that counts down from a preset value to zero, decreasing by one with each clock pulse.
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Feb 29, 2024 - VHDL
Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts
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Nov 23, 2021 - Tcl
Project to show in a BCD display a value set in binary
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Dec 1, 2020 - VHDL
Implementation of a Linear Feedback Shift Register in VHDL and its synthesis on ZyBo Board by Xilinx.
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Nov 16, 2022 - VHDL
Collection of Verilog codes for 6 lab assignments in 2021/1 2110363 Hardware Synthesis Laboratory Course.
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Nov 2, 2021 - Verilog
南理工数字系统综合实验实验代码/实验报告
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Mar 6, 2023 - Verilog
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
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May 17, 2024 - Verilog
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