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Issues list

Compilation issue with aie++
#236 opened Aug 17, 2023 by keryell
@Ralender
3
xrt_piEventGetProfilingInfo not implemented bug Something isn't working
#224 opened Apr 7, 2023 by keryell
@Ralender
Build issue with RHEL8 bug Something isn't working
#192 opened Jul 15, 2022 by jyoung3131
@Ralender
8
There are still some xocc and XOCC in sycl/test/lit.cfg.py
#188 opened Jun 21, 2022 by keryell
@Ralender
1
Implement USM support for XRT plugin enhancement New feature or request
#181 opened May 13, 2022 by keryell
@Ralender
3
Is barrier in kernel supported or going to be supported? enhancement New feature or request
#180 opened May 4, 2022 by fxzjshm
2
Do not generate DDR bank by default if there is no DDR but HBM bug Something isn't working
#176 opened Apr 29, 2022 by keryell
@lforg37
5
fpga_hls_hw_emu fails in vpl step bug Something isn't working
#168 opened Mar 2, 2022 by j-stephan
9
Simplify difference in clang/test/CodeGenSYCL/loop_unroll.cpp
#159 opened Jan 27, 2022 by keryell
@lforg37
1
Handling also sycl::ext::xilinx enhancement New feature or request
#157 opened Jan 27, 2022 by keryell
@lforg37
Adding more small examples from old triSYCL to compare with HLS
#149 opened Oct 23, 2021 by keryell
@lforg37
xilinx::pipeline_kernel not compiling
#148 opened Oct 23, 2021 by keryell
@lforg37
2
Option -fsycl-unnamed-lambda is no longer working bug Something isn't working
#145 opened Oct 22, 2021 by keryell
1
@lforg37 @Ralender
3
Push signed 1-bit integer into C/C++ standard enhancement New feature or request
#141 opened Oct 13, 2021 by keryell
@keryell @lforg37
xilinx::pipeline not providing performance
#136 opened Sep 17, 2021 by ShanoToni
6
Multiple accessor to the same buffer with different ddr_bank property doesn't work bug Something isn't working enhancement New feature or request
#135 opened Sep 16, 2021 by lforg37
@lforg37
1
Rename various symbols to latest Xilinx tools
#122 opened May 25, 2021 by keryell
@lforg37
-Werror breaks toolchain compilation with clang bug Something isn't working
#108 opened Feb 5, 2021 by j-stephan
4
Testing sycl/unified/next branch with path_tracer enhancement New feature or request
#106 opened Feb 5, 2021 by keryell
@lforg37
Add more Xilinx FPGA examples from Xilinx/HLS-Tiny-Tutorials enhancement New feature or request
#104 opened Dec 14, 2020 by keryell
Update /llvm/sycl/doc/Tests.md
#85 opened Sep 29, 2020 by keryell
@keryell
llvm/sycl/test/xocc_tests/disabled/edge_detection example does not work bug Something isn't working
#83 opened Sep 29, 2020 by keryell
2
@Ralender
3
[SYCL] hls's libspir contains unoptimized IR and some buggy IR bug Something isn't working
#78 opened Sep 14, 2020 by Ralender
4
[SYCL][Driver] Refactor xocc driver script back into the LLVM Driver/ToolChain enhancement New feature or request question Further information is requested
#73 opened Nov 8, 2019 by agozillon
How to specify host compiler for xocc? question Further information is requested
#68 opened Sep 18, 2019 by j-stephan
3
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