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Computer-aided VLSI System design (CVSD)

EEE 5022, 2018 Spring, National Taiwan University (NTU)

[Note]:

  1. This course provides training about the flow of digital IC design, including but not limted to RTL coding (Verilog), Synthesis, DFT/ATPG, Static Timing Analysis, Placement and Routing, DRC/LVS, Verification.
  2. Homework Assignments related to RTL coding (Verilog) are available on this repo.

Homework related to RTL coding:

  1. ALU: https://github.com/02stevenyang850527/CVSD/tree/master/hw1
  2. Frequency Analysis System: https://github.com/02stevenyang850527/CVSD/tree/master/hw2
  3. Local Median Filter Engine: https://github.com/02stevenyang850527/CVSD/tree/master/hw3
  4. Digital Photo Album: https://github.com/02stevenyang850527/CVSD/tree/master/final
  5. Formal verification: https://github.com/02stevenyang850527/CVSD/tree/master/hw5