Merge 1ae0a6d on remote branch

Change-Id: Id30067a37fc658da6602837ba3e7ad11e8f2de0e
0ctobot · Aug 19, 2020 · 48b365d · 48b365d
2 parents 93ca81a + 1ae0a6d
commit 48b365d
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Showing 210 changed files with 13,285 additions and 2,387 deletions.
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -127,6 +127,13 @@ Optional properties:
 					turns off PHY pmic power supply, phy ldo and DSI Lane ldo during
 					idle screen (footswitch control off) when this property is enabled.
 - qcom,dsi-phy-regulator-min-datarate-bps:  Minimum per lane data rate (bps) to turn on PHY regulator.
+- frame-threshold-time-us:		For command mode panel, this specifies the idle
+					time for dsi controller where no active data is
+					sent to the panel, as controller is done sending
+					active pixels. If there is no desired DSI clocks
+					specified, then clocks will be derived from this
+					threshold time, which has a default value in chipset
+					based on the CPU processing power.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/graph.txt
@@ -178,6 +185,7 @@ Example:
 		qcom,sync-dual-dsi;
 
 		qcom,mdss-mdp-transfer-time-us = <12000>;
+		frame-threshold-time-us = <800>;
 
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&dsi_active>;

diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
@@ -253,6 +253,7 @@ Optional properties:
 - qcom,mdss-dsi-color-order:		Specifies the R, G and B channel ordering.
 					"rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value)
 					"rgb_swap_rbg" = DSI_RGB_SWAP_RBG
+					"rgb_swap_bgr" = DSI_RGB_SWAP_BGR
 					"rgb_swap_brg" = DSI_RGB_SWAP_BRG
 					"rgb_swap_grb" = DSI_RGB_SWAP_GRB
 					"rgb_swap_gbr" = DSI_RGB_SWAP_GBR
@@ -553,6 +554,7 @@ Optional properties:
 					frequencies in Hz for the given panel.
 - qcom,dsi-dyn-clk-skip-timing-update:	Boolean to specify whether to skip phy timing parameter
 					update during dynamic clock switch.
+- qcom,csi-proxy-enable:		Boolean to config DSI transmission packet DataTypes to simulate the CSI-2 compatible signal
 
 Required properties for sub-nodes:	None
 Optional properties:

diff --git a/Documentation/devicetree/bindings/net/r8125 b/Documentation/devicetree/bindings/net/r8125
@@ -0,0 +1,33 @@
+Realtek  r8125B Ethernet Controller
+
+Required properties:
+
+- compatible : should be "realtek,rtl-8125"
+
+If SMMU is present, also use:
+
+- qcom,smmu : if present, SMMU attach is performed
+- qcom,smmu-iova-base : SMMU IOVA start address the device can access
+- qcom,smmu-iova-size : SMMU IOVA size the device can access
+
+Optional Properties:
+
+- qcom,smmu-attr-fastmap : Enables SMMU fastmap
+- qcom,smmu-attr-atomic : Enables DMA alloc using GFP_ATOMIC
+
+Example:
+
+&pcie_rc0 {
+
+	r8125_x1: qcom,r8125@0 {
+		compatible = realtek,rtl-8125";
+
+		qcom,smmu;
+		qcom,smmu-iova-base = /bits/ 64 <0x0>;
+		qcom,smmu-iova-size = /bits/ 64 <0x100000000>;
+
+		qcom,smmu-attr-atomic;
+		qcom,smmu-attr-fastmap;
+	};
+};
+
diff --git a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt
@@ -80,6 +80,9 @@ Optional properties:
 			identifier.  If this is specified, then a QMP message
 			should be sent to enable the GDSC instead of setting
 			SW_COLLAPSE=0.
+ - qcom,skip-disable-before-sw-enable: Presence denotes a hardware requirement
+					to leave the GDSC on that has been
+					enabled by an entity external to HLOS.
 
 [1]: Documentation/devicetree/bindings/arm/msm/msm_bus.txt
 

diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -1417,6 +1417,8 @@ Optional properties:
 - qcom,afe-rxtx-lb: AFE RX to TX loopback.
 - qcom,ext-mclk-gpio: pinctrl referring to external mclk
 - qcom,ext-mclk-src: Device tree node referring to external mclk clock
+- qcom,pri-spdiftx-gpios: Pinctrl referring to primary spdif output gpios
+- qcom,sec-spdiftx-gpios: Pinctrl referring to secondary spdif output gpios
 - #ext-mclk-1-cfg-cells: Number of cells in ext-mclk-1-cfg-* nodes. Must be 6.
 - ext-mclk-1 cfg-11p2896: Frequnency table for 11.2896MHz mclk frequnecy.
 			  Fields are clock rate, div2x, m, n, d and clock root.

diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig
@@ -365,6 +365,7 @@ CONFIG_RMNET_IPA3=y
 CONFIG_ECM_IPA=y
 CONFIG_RNDIS_IPA=y
 CONFIG_IPA_UT=y
+CONFIG_QCOM_ETHERNET_UTIL=y
 CONFIG_SPMI_PMIC_CLKDIV=y
 CONFIG_MSM_CLK_AOP_QMP=y
 CONFIG_MSM_CLK_RPMH=y

diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig
@@ -376,6 +376,7 @@ CONFIG_RMNET_IPA3=y
 CONFIG_ECM_IPA=y
 CONFIG_RNDIS_IPA=y
 CONFIG_IPA_UT=y
+CONFIG_QCOM_ETHERNET_UTIL=y
 CONFIG_SPMI_PMIC_CLKDIV=y
 CONFIG_MSM_CLK_AOP_QMP=y
 CONFIG_MSM_CLK_RPMH=y

diff --git a/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi b/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -134,6 +134,7 @@
 		qcom,poll-cfg-gdscr;
 		domain-addr = <&gpu_gx_domain_addr>;
 		sw-reset = <&gpu_gx_sw_reset>;
+		qcom,skip-disable-before-sw-enable;
 		status = "disabled";
 	};
 

diff --git a/arch/arm64/boot/dts/qcom/atoll-npu.dtsi b/arch/arm64/boot/dts/qcom/atoll-npu.dtsi
@@ -31,6 +31,7 @@
 		iommus = <&apps_smmu 0x1441 0x0>, <&apps_smmu 0x1442 0x0>,
 			<&apps_smmu 0x1461 0x0>, <&apps_smmu 0x1462 0x0>,
 			<&apps_smmu 0x1481 0x0>, <&apps_smmu 0x1482 0x0>;
+		qcom,npu-dsp-sid-mapped;
 
 		clocks = <&clock_npucc NPU_CC_XO_CLK>,
 			<&clock_npucc NPU_CC_CORE_CLK>,

diff --git a/arch/arm64/boot/dts/qcom/atoll-sde.dtsi b/arch/arm64/boot/dts/qcom/atoll-sde.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -419,6 +419,7 @@
 		compatible = "qcom,dsi-ctrl-hw-v2.4";
 		label = "dsi-ctrl-0";
 		cell-index = <0>;
+		frame-threshold-time-us = <800>;
 		reg =	<0xae94000 0x400>,
 			<0xaf08000 0x4>;
 		reg-names = "dsi_ctrl", "disp_cc_base";

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2015, 2020 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and

diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi
@@ -76,6 +76,22 @@
 		pinctrl-0 = <&ext_mclk_1_sck_active>;
 		pinctrl-1 = <&ext_mclk_1_sck_sleep>;
 	};
+
+	pri_spdiftx_gpios: pri_spdiftx_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&pri_spdiftx_active>;
+		pinctrl-1 = <&pri_spdiftx_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	sec_spdiftx_gpios: sec_spdiftx_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&sec_spdiftx_active>;
+		pinctrl-1 = <&sec_spdiftx_sleep>;
+		qcom,lpi-gpios;
+	};
 };
 
 &q6core {
@@ -109,6 +125,8 @@
 	qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;
 	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;
 	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;
+	qcom,pri-spdiftx-gpios = <&pri_spdiftx_gpios>;
+	qcom,sec-spdiftx-gpios = <&sec_spdiftx_gpios>;
 	qcom,audio-routing =
 		"RX_BIAS", "MCLK",
 		"lineout booster", "LINEOUT1",

diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra8plus2-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra8plus2-audio-overlay.dtsi
@@ -97,6 +97,22 @@
 		pinctrl-0 = <&ext_mclk_1_sck_active>;
 		pinctrl-1 = <&ext_mclk_1_sck_sleep>;
 	};
+
+	pri_spdiftx_gpios: pri_spdiftx_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&pri_spdiftx_active>;
+		pinctrl-1 = <&pri_spdiftx_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	sec_spdiftx_gpios: sec_spdiftx_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&sec_spdiftx_active>;
+		pinctrl-1 = <&sec_spdiftx_sleep>;
+		qcom,lpi-gpios;
+	};
 };
 
 &q6core {
@@ -136,6 +152,8 @@
 	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;
 	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;
 	qcom,quat-mi2s-gpios = <&quat_mi2s_gpios>;
+	qcom,pri-spdiftx-gpios = <&pri_spdiftx_gpios>;
+	qcom,sec-spdiftx-gpios = <&sec_spdiftx_gpios>;
 	qcom,msm-mi2s-master = <1>, <0>, <1>, <0>, <1>, <1>;
 	qcom,audio-routing =
 		"RX_BIAS", "MCLK",

diff --git a/arch/arm64/boot/dts/qcom/qcs405-geni-ir-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-geni-ir-overlay.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -26,6 +26,7 @@
 			<&clock_gcc GCC_GENI_IR_S_CLK>;
 		clock-names = "iface_clk", "serial_clk";
 
+		vdda33-supply = <&pms405_l12>;
 		qcom,geni-ir-wakeup-gpio = <&tlmm 77 IRQ_TYPE_LEVEL_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&ir_in_default>;

diff --git a/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi b/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -453,6 +453,65 @@
 			};
 		};
 
+		pri_spdiftx_pin {
+			pri_spdiftx_sleep: pri_spdiftx_sleep {
+				mux {
+					pins = "gpio6";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <2>;
+					bias-pull-down;
+					output-low;
+				};
+			};
+
+			pri_spdiftx_active: pri_spdiftx_active {
+				mux {
+					pins = "gpio6";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <8>;
+					bias-pull-down;
+					output-low;
+				};
+			};
+		};
+
+		sec_spdiftx_pin {
+			sec_spdiftx_sleep: sec_spdiftx_sleep {
+				mux {
+					pins = "gpio7";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strenght = <2>;
+					bias-bus-hold;
+					output-high;
+				};
+			};
+
+			sec_spdiftx_active: sec_spdiftx_active {
+				mux {
+					pins = "gpio7";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <8>;
+					output-low;
+				};
+			};
+		};
+
 		wsa_swr_data_pin {
 			wsa_swr_data_sleep: wsa_swr_data_sleep {
 				mux {

diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi
@@ -1571,9 +1571,9 @@
 		qcom,msm-bus,num-paths = <2>;
 		qcom,msm-bus,vectors-KBps =
 			<98 512 0 0>, <1 781 0 0>,  /* No vote */
-			<98 512 1250 0>, <1 781 0 40000>,  /* 10Mbps vote */
-			<98 512 12500 0>, <1 781 0 40000>,  /* 100Mbps vote */
-			<98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */
+			<98 512 2500 0>, <1 781 0 40000>,  /* 10Mbps vote */
+			<98 512 25000 0>, <1 781 0 40000>,  /* 100Mbps vote */
+			<98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */
 		qcom,bus-vector-names = "0", "10", "100", "1000";
 		clocks = <&clock_gcc GCC_ETH_AXI_CLK>,
 				<&clock_gcc GCC_ETH_PTP_CLK>,

diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-qcom-smmu.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-qcom-smmu.dtsi
@@ -0,0 +1,38 @@
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+&pcie0_rp {
+	realtek,rtl8125@pcie0_rp {
+		reg = <0 0 0 0 0>;
+
+		compatible = "realtek,rtl-8125";
+
+		pci-ids =
+		   "10ec:8125",
+		   "10ec:3000";
+
+		qcom,smmu;
+
+		/* IOVA range is restricted to avoid conflicts with PCI BAR
+		 * space, Q6 SMEM and IOVA spaces used by peripherals that are
+		 * currently attached to IPA.
+		 */
+		qcom,smmu-iova-base = /bits/ 64 <0x80000000>;
+		qcom,smmu-iova-size = /bits/ 64 <0x0FE40000>;
+
+		qcom,smmu-attr-atomic;
+		qcom,smmu-attr-fastmap;
+
+	};
+};
+
diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi
@@ -155,7 +155,7 @@
 };
 
 &pcie_ep {
-	qcom,pcie-phy-ver = <2102>;
+	qcom,pcie-phy-ver = <2103>;
 	qcom,phy-init = <0x1240 0x001 0x0 0x1
 			0x100c 0x02 0x0 0x1
 			0x1044 0x18 0x0 0x1
@@ -177,6 +177,8 @@
 			0x10bc 0x4b 0x0 0x1
 			0x10c4 0x50 0x0 0x1
 			0x10d4 0x00 0x0 0x1
+			0x10ec 0xfb 0x0 0x1
+			0x10f0 0x01 0x0 0x1
 			0x10f4 0xfb 0x0 0x1
 			0x10f8 0x01 0x0 0x1
 			0x110c 0x02 0x0 0x1
@@ -223,7 +225,7 @@
 			0x0350 0x08 0x0 0x1
 			0x0400 0xa0 0x0 0x1
 			0x043c 0x12 0x0 0x1
-			0x040c 0x12 0x0 0x1
+			0x040c 0x38 0x0 0x1
 			0x0888 0x05 0x0 0x1
 			0x088c 0xf6 0x0 0x1
 			0x0890 0x13 0x0 0x1
@@ -264,6 +266,7 @@
 			0x16f4 0x13 0x0 0x1
 			0x1e24 0x00 0x0 0x1
 			0x1e28 0x00 0x0 0x1
+			0x1388 0x77 0x0 0x1
 			0x1200 0x000 0x0 0x1
 			0x1244 0x003 0x0 0x1>;
 };