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This commit fleshes out the HQM driver with full support for the physical function device, including - ioctl interface: through a device file, the driver provides ioctls for device configuration and measurement. The ioctl interface is versioned and designed for backwards compatibility and extensibility. - mmap interface: the driver provides an mmap callback which makes a subset of the device accessible directly from user-space, which enables device enqueue and dequeue operations without a syscall. - read interface: applications can read() the device file to receive alerts from the device driver. - sysfs interface: applications can use the sysfs interface to query resource availability and further tune the device. - CQ interrupts: the driver supports interrupt-driven applications in addition to polling-driven application. - Dynamic power management: the device is put into D3Hot when no applications are using it. Signed-off-by: Gage Eads <gage.eads@intel.com>
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,83 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only | ||
| * Copyright(c) 2017-2019 Intel Corporation | ||
| */ | ||
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| #ifndef __HQM_OPS_DP_H | ||
| #define __HQM_OPS_DP_H | ||
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| #include <linux/frame.h> | ||
| #include <asm/fpu/api.h> | ||
| #include <asm/cpu.h> | ||
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| /* CPU feature enumeration macros */ | ||
| #define CPUID_DIRSTR_BIT 27 | ||
| #define CPUID_DIRSTR64B_BIT 28 | ||
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| static inline bool movdir64b_supported(void) | ||
| { | ||
| int eax, ebx, ecx, edx; | ||
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| asm volatile("mov $7, %%eax\t\n" | ||
| "mov $0, %%ecx\t\n" | ||
| "cpuid\t\n" | ||
| : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)); | ||
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| return ecx & (1 << CPUID_DIRSTR64B_BIT); | ||
| } | ||
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| /** | ||
| * movntdq_asm() - execute a movntdq instruction | ||
| * @addr: mapped producer port address | ||
| * @data0: least-significant 8B to move | ||
| * @data1: most-significant 8B to move | ||
| * | ||
| * This function executes movntdq, moving @data0 and @data1 into the address | ||
| * @addr. | ||
| */ | ||
| static inline void movntdq_asm(long long __iomem *addr, | ||
| long long data0, | ||
| long long data1) | ||
| { | ||
| #ifdef CONFIG_AS_SSE2 | ||
| __asm__ __volatile__("movq %1, %%xmm0\n" | ||
| "movhps %2, %%xmm0\n" | ||
| "movntdq %%xmm0, %0" | ||
| : "=m" (*addr) : "r" (data0), "m" (data1)); | ||
| #endif | ||
| } | ||
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| static inline void hqm_movntdq(void *qe4, void __iomem *pp_addr) | ||
| { | ||
| /* Move entire 64B cache line of QEs, 128 bits (16B) at a time. */ | ||
| long long *_qe = (long long *)qe4; | ||
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| kernel_fpu_begin(); | ||
| movntdq_asm(pp_addr + 0, _qe[0], _qe[1]); | ||
| /* (see comment below) */ | ||
| wmb(); | ||
| movntdq_asm(pp_addr + 0, _qe[2], _qe[3]); | ||
| /* (see comment below) */ | ||
| wmb(); | ||
| movntdq_asm(pp_addr + 0, _qe[4], _qe[5]); | ||
| /* (see comment below) */ | ||
| wmb(); | ||
| movntdq_asm(pp_addr + 0, _qe[6], _qe[7]); | ||
| kernel_fpu_end(); | ||
| /* movntdq requires an sfence between writes to the PP MMIO address */ | ||
| wmb(); | ||
| } | ||
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| static inline void hqm_movdir64b(void *qe4, void __iomem *pp_addr) | ||
| { | ||
| asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" | ||
| : | ||
| : "a" (pp_addr), "d" (qe4)); | ||
| } | ||
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| /* objtool's instruction decoder doesn't recognize the hard-coded machine | ||
| * instructions for movdir64b, which causes it to emit "undefined stack state" | ||
| * and "falls through" warnings. For now, ignore the functions. | ||
| */ | ||
| STACK_FRAME_NON_STANDARD(hqm_movdir64b); | ||
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| #endif /* __HQM_OPS_DP_H */ |
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