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platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc…
… subfolder As part of collecting Intel x86 specific drivers in their own folder, move intel_pmc_core* files to its own subfolder there. Cc: Chao Qin <chao.qin@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: David Box <david.e.box@intel.com> Cc: You-Sheng Yang <vicamo.yang@canonical.com> Cc: Hans de Goede <hdegoede@redhat.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
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# SPDX-License-Identifier: GPL-2.0-only | ||
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config INTEL_PMC_CORE | ||
tristate "Intel PMC Core driver" | ||
depends on PCI | ||
depends on ACPI | ||
help | ||
The Intel Platform Controller Hub for Intel Core SoCs provides access | ||
to Power Management Controller registers via various interfaces. This | ||
driver can utilize debugging capabilities and supported features as | ||
exposed by the Power Management Controller. It also may perform some | ||
tasks in the PMC in order to enable transition into the SLPS0 state. | ||
It should be selected on all Intel platforms supported by the driver. | ||
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Supported features: | ||
- SLP_S0_RESIDENCY counter | ||
- PCH IP Power Gating status | ||
- LTR Ignore / LTR Show | ||
- MPHY/PLL gating status (Sunrise Point PCH only) | ||
- SLPS0 Debug registers (Cannon Lake/Ice Lake PCH) | ||
- Low Power Mode registers (Tiger Lake and beyond) | ||
- PMC quirks as needed to enable SLPS0/S0ix |
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# SPDX-License-Identifier: GPL-2.0 | ||
# | ||
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o | ||
intel_pmc_core-objs := core.o \ | ||
core_platform.o |
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