drm_cache: Add logic for wbvind_on_all_cpus

Add logic for wbvind_on_all_cpus for non-x86 platforms. v2(Michael Cheng): Change logic to if platform is not x86, then we add pr_warn for calling wbvind_on_all_cpus. Signed-off-by: Michael Cheng <michael.cheng@intel.com>
0day-ci · Feb 22, 2022 · 3aaa40c · 3aaa40c
1 parent 55223c3
commit 3aaa40c
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
@@ -40,8 +40,6 @@
 #define MEMCPY_BOUNCE_SIZE 128
 
 #if defined(CONFIG_X86)
-#include <asm/smp.h>
-
 /*
  * clflushopt is an unordered instruction which needs fencing with mfence or
  * sfence to avoid ordering issues.  For drm_clflush_page this fencing happens

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
@@ -34,6 +34,12 @@
 #define _DRM_CACHE_H_
 
 #include <linux/scatterlist.h>
+#include <asm/smp.h>
+
+#if !defined(CONFIG_x86)
+#define wbinvd_on_all_cpus() \
+	pr_warn("Missing cache flush in %s\n", __func__)
+#endif
 
 struct iosys_map;