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media: platform: mtk-mdp3: add Mediatek MDP3 driver
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This patch adds driver for Mediatek's Media Data Path ver.3 (MDP3).
It provides the following functions:
  color transform, format conversion, resize, crop, rotate, flip
  and additional image quality enhancement.

The MDP3 driver is mainly used for Google Chromebook products to
import the new architecture to set the HW settings as shown below:
  User -> V4L2 framework
    -> MDP3 driver -> SCP (setting calculations)
      -> MDP3 driver -> CMDQ (GCE driver) -> HW

Each modules' related operation control is sited in mtk-mdp3-comp.c
Each modules' register table is defined in file with "mdp_reg_" prefix
GCE related API, operation control  sited in mtk-mdp3-cmdq.c
V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
Probe, power, suspend/resume, system level functions are defined in
mtk-mdp3-core.c

Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
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@MoudyHo @intel-lab-lkp
MoudyHo authored and intel-lab-lkp committed Oct 15, 2021
1 parent d651f0a commit 6714c53
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Showing 22 changed files with 5,328 additions and 0 deletions.
19 changes: 19 additions & 0 deletions drivers/media/platform/Kconfig
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Expand Up @@ -299,6 +299,25 @@ config VIDEO_MEDIATEK_MDP
To compile this driver as a module, choose M here: the
module will be called mtk-mdp.

config VIDEO_MEDIATEK_MDP3
tristate "Mediatek MDP v3 driver"
depends on MTK_IOMMU || COMPLIE_TEST
depends on VIDEO_DEV && VIDEO_V4L2
depends on ARCH_MEDIATEK || COMPILE_TEST
depends on HAS_DMA
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
select VIDEO_MEDIATEK_VPU
select MTK_CMDQ
select MTK_SCP
default n
help
It is a v4l2 driver and present in Mediatek MT8183 SoC.
The driver supports for scaling and color space conversion.

To compile this driver as a module, choose M here: the
module will be called mtk-mdp3.

config VIDEO_MEDIATEK_VCODEC
tristate "Mediatek Video Codec driver"
depends on MTK_IOMMU || COMPILE_TEST
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2 changes: 2 additions & 0 deletions drivers/media/platform/Makefile
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Expand Up @@ -77,6 +77,8 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) += mtk-vcodec/

obj-$(CONFIG_VIDEO_MEDIATEK_MDP) += mtk-mdp/

obj-$(CONFIG_VIDEO_MEDIATEK_MDP3) += mtk-mdp3/

obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk-jpeg/

obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
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6 changes: 6 additions & 0 deletions drivers/media/platform/mtk-mdp3/Makefile
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@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
mtk-mdp3-y += mtk-mdp3-core.o mtk-mdp3-vpu.o mtk-mdp3-regs.o
mtk-mdp3-y += mtk-mdp3-m2m.o
mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o

obj-$(CONFIG_VIDEO_MEDIATEK_MDP3) += mtk-mdp3.o
19 changes: 19 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __MDP_REG_CCORR_H__
#define __MDP_REG_CCORR_H__

#define MDP_CCORR_EN 0x000
#define MDP_CCORR_CFG 0x020
#define MDP_CCORR_SIZE 0x030

/* MASK */
#define MDP_CCORR_EN_MASK 0x00000001
#define MDP_CCORR_CFG_MASK 0x70001317
#define MDP_CCORR_SIZE_MASK 0x1fff1fff

#endif // __MDP_REG_CCORR_H__
27 changes: 27 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
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@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __ISP_REG_H__
#define __ISP_REG_H__

enum isp_dip_cq {
ISP_DRV_DIP_CQ_THRE0 = 0,
ISP_DRV_DIP_CQ_THRE1,
ISP_DRV_DIP_CQ_THRE2,
ISP_DRV_DIP_CQ_THRE3,
ISP_DRV_DIP_CQ_THRE4,
ISP_DRV_DIP_CQ_THRE5,
ISP_DRV_DIP_CQ_THRE6,
ISP_DRV_DIP_CQ_THRE7,
ISP_DRV_DIP_CQ_THRE8,
ISP_DRV_DIP_CQ_THRE9,
ISP_DRV_DIP_CQ_THRE10,
ISP_DRV_DIP_CQ_THRE11,
ISP_DRV_DIP_CQ_NUM,
ISP_DRV_DIP_CQ_NONE,
};

#endif // __ISP_REG_H__
65 changes: 65 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
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@@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __MDP_REG_RDMA_H__
#define __MDP_REG_RDMA_H__

#define MDP_RDMA_EN 0x000
#define MDP_RDMA_RESET 0x008
#define MDP_RDMA_CON 0x020
#define MDP_RDMA_GMCIF_CON 0x028
#define MDP_RDMA_SRC_CON 0x030
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
#define MDP_RDMA_MF_SRC_SIZE 0x070
#define MDP_RDMA_MF_CLIP_SIZE 0x078
#define MDP_RDMA_MF_OFFSET_1 0x080
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
#define MDP_RDMA_SRC_END_0 0x100
#define MDP_RDMA_SRC_END_1 0x108
#define MDP_RDMA_SRC_END_2 0x110
#define MDP_RDMA_SRC_OFFSET_0 0x118
#define MDP_RDMA_SRC_OFFSET_1 0x120
#define MDP_RDMA_SRC_OFFSET_2 0x128
#define MDP_RDMA_SRC_OFFSET_0_P 0x148
#define MDP_RDMA_TRANSFORM_0 0x200
#define MDP_RDMA_RESV_DUMMY_0 0x2a0
#define MDP_RDMA_MON_STA_1 0x408
#define MDP_RDMA_SRC_BASE_0 0xf00
#define MDP_RDMA_SRC_BASE_1 0xf08
#define MDP_RDMA_SRC_BASE_2 0xf10
#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y 0xf20
#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C 0xf28

/* MASK */
#define MDP_RDMA_EN_MASK 0x00000001
#define MDP_RDMA_RESET_MASK 0x00000001
#define MDP_RDMA_CON_MASK 0x00001110
#define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771
#define MDP_RDMA_SRC_CON_MASK 0xf3ffffff
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff
#define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
#define MDP_RDMA_SRC_END_0_MASK 0xffffffff
#define MDP_RDMA_SRC_END_1_MASK 0xffffffff
#define MDP_RDMA_SRC_END_2_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_0_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_1_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_2_MASK 0xffffffff
#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y_MASK 0xffffffff
#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C_MASK 0xffffffff

#endif // __MDP_REG_RDMA_H__
39 changes: 39 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
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@@ -0,0 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __MDP_REG_RSZ_H__
#define __MDP_REG_RSZ_H__

#define PRZ_ENABLE 0x000
#define PRZ_CONTROL_1 0x004
#define PRZ_CONTROL_2 0x008
#define PRZ_INPUT_IMAGE 0x010
#define PRZ_OUTPUT_IMAGE 0x014
#define PRZ_HORIZONTAL_COEFF_STEP 0x018
#define PRZ_VERTICAL_COEFF_STEP 0x01c
#define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
#define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
#define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034

/* MASK */
#define PRZ_ENABLE_MASK 0x00010001
#define PRZ_CONTROL_1_MASK 0xfffffff3
#define PRZ_CONTROL_2_MASK 0x0ffffaff
#define PRZ_INPUT_IMAGE_MASK 0xffffffff
#define PRZ_OUTPUT_IMAGE_MASK 0xffffffff
#define PRZ_HORIZONTAL_COEFF_STEP_MASK 0x007fffff
#define PRZ_VERTICAL_COEFF_STEP_MASK 0x007fffff
#define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
#define PRZ_LUMA_VERTICAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff

#endif // __MDP_REG_RSZ_H__
47 changes: 47 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
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@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __MDP_REG_WDMA_H__
#define __MDP_REG_WDMA_H__

#define WDMA_EN 0x008
#define WDMA_RST 0x00c
#define WDMA_CFG 0x014
#define WDMA_SRC_SIZE 0x018
#define WDMA_CLIP_SIZE 0x01c
#define WDMA_CLIP_COORD 0x020
#define WDMA_DST_W_IN_BYTE 0x028
#define WDMA_ALPHA 0x02c
#define WDMA_BUF_CON2 0x03c
#define WDMA_DST_UV_PITCH 0x078
#define WDMA_DST_ADDR_OFFSET 0x080
#define WDMA_DST_U_ADDR_OFFSET 0x084
#define WDMA_DST_V_ADDR_OFFSET 0x088
#define WDMA_FLOW_CTRL_DBG 0x0a0
#define WDMA_DST_ADDR 0xf00
#define WDMA_DST_U_ADDR 0xf04
#define WDMA_DST_V_ADDR 0xf08

/* MASK */
#define WDMA_EN_MASK 0x00000001
#define WDMA_RST_MASK 0x00000001
#define WDMA_CFG_MASK 0xff03bff0
#define WDMA_SRC_SIZE_MASK 0x3fff3fff
#define WDMA_CLIP_SIZE_MASK 0x3fff3fff
#define WDMA_CLIP_COORD_MASK 0x3fff3fff
#define WDMA_DST_W_IN_BYTE_MASK 0x0000ffff
#define WDMA_ALPHA_MASK 0x800000ff
#define WDMA_BUF_CON2_MASK 0xffffffff
#define WDMA_DST_UV_PITCH_MASK 0x0000ffff
#define WDMA_DST_ADDR_OFFSET_MASK 0x0fffffff
#define WDMA_DST_U_ADDR_OFFSET_MASK 0x0fffffff
#define WDMA_DST_V_ADDR_OFFSET_MASK 0x0fffffff
#define WDMA_FLOW_CTRL_DBG_MASK 0x0000f3ff
#define WDMA_DST_ADDR_MASK 0xffffffff
#define WDMA_DST_U_ADDR_MASK 0xffffffff
#define WDMA_DST_V_ADDR_MASK 0xffffffff

#endif // __MDP_REG_WDMA_H__
55 changes: 55 additions & 0 deletions drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
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@@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
*/

#ifndef __MDP_REG_WROT_H__
#define __MDP_REG_WROT_H__

#define VIDO_CTRL 0x000
#define VIDO_MAIN_BUF_SIZE 0x008
#define VIDO_SOFT_RST 0x010
#define VIDO_SOFT_RST_STAT 0x014
#define VIDO_CROP_OFST 0x020
#define VIDO_TAR_SIZE 0x024
#define VIDO_OFST_ADDR 0x02c
#define VIDO_STRIDE 0x030
#define VIDO_OFST_ADDR_C 0x038
#define VIDO_STRIDE_C 0x03c
#define VIDO_DITHER 0x054
#define VIDO_STRIDE_V 0x06c
#define VIDO_OFST_ADDR_V 0x068
#define VIDO_RSV_1 0x070
#define VIDO_IN_SIZE 0x078
#define VIDO_ROT_EN 0x07c
#define VIDO_FIFO_TEST 0x080
#define VIDO_MAT_CTRL 0x084
#define VIDO_BASE_ADDR 0xf00
#define VIDO_BASE_ADDR_C 0xf04
#define VIDO_BASE_ADDR_V 0xf08

/* MASK */
#define VIDO_CTRL_MASK 0xf530711f
#define VIDO_MAIN_BUF_SIZE_MASK 0x1fff7f77
#define VIDO_SOFT_RST_MASK 0x00000001
#define VIDO_SOFT_RST_STAT_MASK 0x00000001
#define VIDO_TAR_SIZE_MASK 0x1fff1fff
#define VIDO_CROP_OFST_MASK 0x1fff1fff
#define VIDO_OFST_ADDR_MASK 0x0fffffff
#define VIDO_STRIDE_MASK 0x0000ffff
#define VIDO_OFST_ADDR_C_MASK 0x0fffffff
#define VIDO_STRIDE_C_MASK 0x0000ffff
#define VIDO_DITHER_MASK 0xff000001
#define VIDO_STRIDE_V_MASK 0x0000ffff
#define VIDO_OFST_ADDR_V_MASK 0x0fffffff
#define VIDO_RSV_1_MASK 0xffffffff
#define VIDO_IN_SIZE_MASK 0x1fff1fff
#define VIDO_ROT_EN_MASK 0x00000001
#define VIDO_FIFO_TEST_MASK 0x00000fff
#define VIDO_MAT_CTRL_MASK 0x000000f3
#define VIDO_BASE_ADDR_MASK 0xffffffff
#define VIDO_BASE_ADDR_C_MASK 0xffffffff
#define VIDO_BASE_ADDR_V_MASK 0xffffffff

#endif // __MDP_REG_WROT_H__

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