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drm/mipi-dbi: Add support for Type B
Intel 8080 type (Type B) parallel bus over GPIO. The parallel bus is implemented partially. It supports only write operations from the host to the display. Read operations would require switching GPIO mode between input and output back and forth. But this implementation is very simple, and GPIO mode can be set for all used pins to output once at initialization. It is enough to support only write operations to initialize displays and output video data. The bus driver returns EOPNOTSUPP for all read operations requested through a display driver. Bit banging is used to transmit data over the parallel bus from host to display. There are two numbers that contol timings: wr_up_delay and wr_down_delay. They should be provided by the display driver. The first number is related to the write control pulse duration, and the second number is related to the write cycle duration that can be found in the specification of the display. Signed-off-by: Mikhail Durnev <mikhail_durnev@mentor.com>
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