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clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only difference being RZ/V2L has an additional registers to control clock and reset for the DRP-AI block. This patch reuses r9a07g044-cpg.c, as the common clock IDS and rest IDS are same between RZ/G2L and RZ/V2L and adding a separate r9a07g054_cpg_info to take care of DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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