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clk: Add ccf driver for Renesas 8T49N241
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This is a common clock framework driver that supports the 8T49N241 chip.
No other chips in the family are currently supported. The driver
supports setting the rate for all four outputs on the chip and
automatically calculating/setting the appropriate VCO value.

The driver can read a full register map from the device tree
and will use that register map to initialize the attached device
(via I2C) when the system boots. Any configuration not supported by
the common clock framework must be done via the full register map,
including optimized settings.

All outputs are currently assumed to be LVDS unless overridden in
the full register map in the DT.

Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
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Alex Helms authored and intel-lab-lkp committed Jul 1, 2021
1 parent 57be95a commit e0b191d
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1 change: 1 addition & 0 deletions MAINTAINERS
Original file line number Diff line number Diff line change
Expand Up @@ -15569,6 +15569,7 @@ M: Alex Helms <alexander.helms.jy@renesas.com>
M: David Cater <david.cater.jc@renesas.com>
S: Odd Fixes
F: Documentation/devicetree/bindings/clock/renesas,8t49n241.yaml
F: drivers/clk/renesas/8t49n24x*

RENESAS CLOCK DRIVERS
M: Geert Uytterhoeven <geert+renesas@glider.be>
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21 changes: 21 additions & 0 deletions drivers/clk/Kconfig
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Expand Up @@ -330,6 +330,27 @@ config COMMON_CLK_VC5
This driver supports the IDT VersaClock 5 and VersaClock 6
programmable clock generators.

config COMMON_CLK_8T49N24X
tristate "Clock driver for Renesas 8T49N24x"
depends on I2C
depends on OF
select REGMAP_I2C
help
This driver supports the Renesas 8T49N24x universal frequency
translator product family. The only chip in the family that is currently
supported is the 8T49N241. The driver supports setting the rate for
all four outputs on the chip and automatically calculating/setting
the appropriate VCO value.

The driver can read a full register map from the DT,
and will use that register map to initialize the attached part
(via I2C) when the system boots. Any configuration not supported
by the common clock framework must be done via the full register
map, including optimized settings.

All outputs are currently assumed to be LVDS, unless overridden
in the full register map in the DT.

config COMMON_CLK_STM32MP157
def_bool COMMON_CLK && MACH_STM32MP157
help
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