Address comment

0xPolygonMiden · Jan 17, 2022 · 2afc225 · 2afc225
1 parent 10ca65d
commit 2afc225
Showing 1 changed file with 18 additions and 6 deletions.
diff --git a/assembly/src/parsers/u32_ops.rs b/assembly/src/parsers/u32_ops.rs
@@ -189,23 +189,33 @@ pub fn parse_u32xor(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), Ass
     Ok(())
 }
 
-/// Translates u32not assembly instruction to VM operation PAD U32OR SWAP U32XOR.
+/// Translates u32not assembly instruction to VM operation PUSH(2^32) SWAP INCR U32SUB.
+/// The reason this works is because 2^32 provides a bit mask of ones, which after
+/// subtracting the element, flips the bits of the original value to perform a bitwise NOT.
 pub fn parse_u32not(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), AssemblyError> {
     match op.num_parts() {
         0 => return Err(AssemblyError::missing_param(op)),
         1 => {
+            // Assert the value is u32
+            span_ops.push(Operation::U32split);
+            span_ops.push(Operation::Not);
+            span_ops.push(Operation::Assert);
+
             span_ops.push(Operation::Push(BaseElement::new(2 ^ 32)));
             span_ops.push(Operation::Swap);
             span_ops.push(Operation::Incr);
             span_ops.push(Operation::U32sub);
+
+            // Drop the underflow flag
+            span_ops.push(Operation::Drop);
         }
         _ => return Err(AssemblyError::extra_param(op)),
     }
 
     Ok(())
 }
 
-/// Translates u32shl.x assembly instruction to VM operation PUSH(2^x) MUL U32DIV DROP.
+/// Translates u32shl.x assembly instruction to VM operation PUSH(2^x) MUL U32SPLIT DROP.
 pub fn parse_u32shl(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), AssemblyError> {
     match op.num_parts() {
         0..=1 => return Err(AssemblyError::missing_param(op)),
@@ -218,7 +228,7 @@ pub fn parse_u32shl(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), Ass
             let x = parse_int_param(op, 1, 1, 31)?;
             span_ops.push(Operation::Push(BaseElement::new(2u64.pow(x))));
             span_ops.push(Operation::Mul);
-            span_ops.push(Operation::U32div);
+            span_ops.push(Operation::U32split);
             span_ops.push(Operation::Drop);
         }
         _ => return Err(AssemblyError::extra_param(op)),
@@ -227,7 +237,7 @@ pub fn parse_u32shl(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), Ass
     Ok(())
 }
 
-/// Translates u32shl.x assembly instruction to VM operation PUSH(2^x) U32DIV U32DIV DROP.
+/// Translates u32shl.x assembly instruction to VM operation PUSH(2^x) U32DIV SWAP DROP.
 pub fn parse_u32shr(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), AssemblyError> {
     match op.num_parts() {
         0..=1 => return Err(AssemblyError::missing_param(op)),
@@ -281,11 +291,13 @@ pub fn parse_u32eq(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), Asse
 
             span_ops.push(Operation::Swap);
 
-            // Check first number is u32
+            // Check second number is u32
             span_ops.push(Operation::U32split);
             span_ops.push(Operation::Not);
             span_ops.push(Operation::Assert);
 
+            span_ops.push(Operation::Swap);
+
             span_ops.push(Operation::Eq);
         }
         _ => return Err(AssemblyError::extra_param(op)),
@@ -308,7 +320,7 @@ pub fn parse_u32neq(span_ops: &mut Vec<Operation>, op: &Token) -> Result<(), Ass
 
             span_ops.push(Operation::Swap);
 
-            // Check first number is u32
+            // Check second number is u32
             span_ops.push(Operation::U32split);
             span_ops.push(Operation::Not);
             span_ops.push(Operation::Assert);