This is a python based script that can generate system verilog codes of pipelined adder tree.There are two configurable parameters in this script:DATA_WIDTH and N. DATA_WIDTH means the data width of input and output; N means the input data number of the adder tree,currently only support N to be power of two.
To use this script,just input
python -W your_data_width -N your_input_data_num
Then you can find three system verilog source files in current path.They are adder.sv,adderTree.sv and test_tb.sv.The first two are source files,and the last one is testbench.
Take N=32,W=64 as example,the RTL View is as below:
