This is Moscovium series MCU projects for Sipeed Lichee Tang Primer FPGA board.
- Anlogic TD IDE project
- Development on this FPGA board (Primer) has been frozen.
- Development is progressing on another FPGA board (Cmod A7).
- See MCOC115-VD repository.
- MCOC: Moscovium (Mc) On Chip
- 115 is the atomic number of Mc (Moscovium).
- 117 for Ts (Tennessine), 113 for Nh (Nihonium).
Moscovium is an original 16 bit CPU core.
More options for the Moscovium series here:
- Tennessine
- 8 bit data path
- Moscovium
- 16 bit data path
- Moscovium-SS
- 16 bit data path x2
- Super Scalar
- Nihonium
- 32 bit data path
- Nihonium-SS
- 32 bit data path x2
- Super Scalar
Moscovium series CPU cores are scalable from 8 ~ 32 bit data paths.
- The order listed above is roughly a trade-off between performance and size (LUTs).
- Lower performance takes smaller size.
- Higher performance takes larger size.
- README.md
- This article.
- MCOC115/
- Anlogic TD IDE's project directory
- al_ip/
- Anlogic IP files
- asmsrc/
- Assembler and sample sources
- ip/
- IP units
- simulation/
- Test bench for logic simulation
- top/
- Top level modules
- *.al
- TD IDE's project file
- See MCU edition table MCOC_edition.png.
- al_ip/
- Anlogic TD IDE's project directory
- LIBAL/
- Anlogic TD IDE cell library
- al/
- ef2/
- ef3/
- eg/
- elf/
- Anlogic TD IDE cell library
Copy all the files under "sim/" in the TD IDE installation directory to "LIBAL/" by yourself.
- <InstallDir>/Anlogic/TD4.6.4/sim/ ==copy=> LIBAL/
- al/
- ef2/
- ef3/
- eq/
- elf/
For details in Japanese, please see the following URL.
Comment out "`resetall" directive at the beginning of following files.
- LIBAL/al/al_map_addr.v
- LIBAL/al/al_map_mux4.v
See MCU edition table MCOC_edition.png first.
All links point to Japanese pages.
- Moscovium
- Original 16 bit CPU core
- Moscovium-SS
- Original 16 bit CPU core
- Super Scalar edition
- Nihonium
- Original 32 bit CPU core
- Nihonium-SS
- Original 32 bit CPU core
- Super Scalar edition
- Tennessine
- Original 8 bit CPU core
- MULC16
- Multiply coprocessor
- for Moscovium / Moscovium-SS
- 16 * 16 = 32 bit multiply, signed and unsigned
- Multiply coprocessor
- DIVC32
- Divide coprocessor
- for Moscovium / Moscovium-SS
- 16 / 16 = 16 ... 16 bit divide, signed and unsigned
- 32 / 32 = 32 ... 32 bit divide, signed and unsigned
- Divide coprocessor
- HALFPU
- 16 bit half precision Floating Point Unit (FPU)
- for Moscovium / Moscovium-SS / Nihonium / Nihonium-SS
- 16 bit half precision Floating Point Unit (FPU)
- SGLFPU
- 32 bit single precision Floating Point Unit (FPU)
- for Nihonium / Nihonium-SS
- 32 bit single precision Floating Point Unit (FPU)
- BUSC2040DL
- Bus state controller
- 24 bit address area, 16 / 32 bit data bus
- INTC322DVL
- Interrupt controller
- 4 level vector interrupt
- CACHE2W4K
- Cache memory controller
- 2 way set associative, 4K byte, LFU, write through
- SYSTIM
- System timer unit
- Millisecond, microsecond and clock counter
- TIM162
- 16 bit PWM timer unit
- 2 PWM output
- RTC400
- Real time clock unit
- Full 400 years of leap year support
- UART8N1
- UART unit
- Format: 8N1 (8 bit data, no parity, 1 stop bit)
- STWSER
- Synchronous two wire serial unit (I2C)
- Master and slave communication
- PORT8I8O
- General I/O port unit
- IOMEM16
- 16 byte I/O memory (RAM) unit
- SEMPH5R9U
- Semaphore unit
- ICFF16
- Intercommunication FIFO unit
- LOGA8CH
- Logic analyzer accelerator unit
- FONTJP
- Japanese font unit
- ADC124
- 12 bit SAR A/D converter unit
- DAC121
- 12 bit delta-sigma D/A converter unit
- UNISJI
- Unicode and S-JIS conversion unit
- DISTUS
- Distance measuring by ultrasonic sensor unit
- ROM
- Instruction ROM unit
- IRAM
- Instruction RAM unit
- RAM
- Main memory (RAM) unit
- SDRAM8M
- Builtin SDRAM unit
Select "<>Code => Local => Download ZIP".
Unzip down loaded file.
You can see documentation in Japanese from links below.
- Moscovium series MCU (http://hello.world.coocan.jp/ARDUINO15/a153_instset.html#LINEUP)
- Instruction set manual (http://hello.world.coocan.jp/ARDUINO15/a153_instset.html#MANTOP)
- FPGA board pin assignment (http://hello.world.coocan.jp/ARDUINO15/a153_mcoc115.html)
- Simulation (http://hello.world.coocan.jp/ARDUINO15/arduino15_1.html#VERILOG)
- Programming (configure) to FPGA board (http://hello.world.coocan.jp/ARDUINO15/a153_design.html#BURNFPGA)
- FPGA board
- Sipeed Lichee Tang Primer (https://tang.sipeed.com/en/)
- Anlogic EG4S20 FPGA chip (https://tang.sipeed.com/en/hardware-overview/lichee-tang/)
All data in this repository are unsupported and unguaranteed.
Use at your own risk.