-
Notifications
You must be signed in to change notification settings - Fork 0
/
MainMem.bsv
76 lines (61 loc) · 2.01 KB
/
MainMem.bsv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
import RVUtil::*;
import BRAM::*;
import FIFO::*;
import SpecialFIFOs::*;
import DelayLine::*;
import MemTypes::*;
interface MainMem;
method Action put(MainMemReq req);
method ActionValue#(MainMemResp) get();
endinterface
interface MainMemFast;
method Action put(CacheReq req);
method ActionValue#(Word) get();
endinterface
module mkMainMemFast(MainMemFast);
BRAM_Configure cfg = defaultValue();
cfg.loadFormat = tagged Hex "mem.vmh";
BRAM1PortBE#(Bit#(30), Word, 4) bram <- mkBRAM1ServerBE(cfg);
DelayLine#(10, Word) dl <- mkDL(); // Delay by 20 cycles
rule deq;
let r <- bram.portA.response.get();
dl.put(r);
// $display("REF RESP", fshow(r));
endrule
method Action put(CacheReq req);
// $display("REF REQ", fshow(req));
bram.portA.request.put(BRAMRequestBE{
writeen: req.word_byte,
responseOnWrite: False,
address: req.addr[31:2],
datain: req.data});
endmethod
method ActionValue#(Word) get();
let r <- dl.get();
return r;
endmethod
endmodule
module mkMainMem(MainMem);
BRAM_Configure cfg = defaultValue();
cfg.loadFormat = tagged Hex "memlines.vmh";
BRAM1Port#(Bit#(26), MainMemResp) bram <- mkBRAM1Server(cfg); // spoilers!
DelayLine#(20, MainMemResp) dl <- mkDL(); // Delay by 20 cycles
rule deq;
let r <- bram.portA.response.get();
dl.put(r);
// $display("GOT FROM MM TO DL1 ",fshow(r));
endrule
method Action put(MainMemReq req);
bram.portA.request.put(BRAMRequest{
write: unpack(req.write),
responseOnWrite: False,
address: req.addr,
datain: req.data});
// $display("SENT TO MM1 WITH ",fshow(req));
endmethod
method ActionValue#(MainMemResp) get();
let r <- dl.get();
//$display("GOT FROM DL1 TO CACHE ",fshow(r));
return r;
endmethod
endmodule