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msm: acpuclok-8064: 1700Mhz table back to stock voltages
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reverting "undervolt 1700Mhz table" due to added user voltage control.
In future everyone should set their undervolt on their own,
if wanted. If not, leave it stock :p

reverts commit afc96f1.
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@9Lukas5
9Lukas5 committed Mar 30, 2016
1 parent aecb8d6 commit f99daf2
Showing 1 changed file with 98 additions and 98 deletions.
196 changes: 98 additions & 98 deletions arch/arm/mach-msm/acpuclock-8064.c
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Expand Up @@ -351,128 +351,128 @@ static struct acpu_level tbl_PVS6_1512MHz[] __initdata = {
};

static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 900000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 912500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 925000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 950000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 962500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 987500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1000000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1062500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1150000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1175000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1225000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 987500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1025000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1050000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1087500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1112500 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1150000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1187500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 850000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 850000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 850000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 850000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 875000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 900000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 925000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 937500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 950000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1012500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1050000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1085000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1162500 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 825000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 825000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 825000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 837500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 850000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 875000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 900000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 912500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 925000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 950000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 987500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 825000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 825000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 825000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 837500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 850000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 875000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 900000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 912500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 925000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 950000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 987500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 825000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 825000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 825000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 837500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 850000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 875000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 887500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 900000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 912500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 937500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 962500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1000000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1025000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(2), 825000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 825000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 825000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 837500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 850000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(12), 875000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 887500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 900000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 912500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 925000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 950000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 975000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1000000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
{ 0, { 0 } }
};

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