Combinatorial Logic Unsigned Integer Array Divider Generator

Introduction

This project contians a Python script designed to automatically generate Verilog code for a combinatorial logic unsigned integer array divider.

⚠️ DO NOT USE THIS GENERATOR IN YOUR REAL PROJECT

Combinatorial logic dividers can consume significant resources and result in substantial delays. Just for fun :)

If you really need a high-preformance divider, use ip core instead.

Prerequisites

• Python 3.x
• Text editor or integrated development environment (IDE)

Usage

1. Clone or download the code repository for this project.

2. Run the generation script:

   python generate.py
   

   Then input the width you need, max 99 bit. This will create a Verilog file containing the generated digital circuit description verilog.