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RTX5: rename IRQ modules to match architecture (#943)
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irq_cm0.S  -> irq_armv6m.S
irq_cm3.S  -> irq_armv7m.S
irq_cm4f.S -> irq_armv7m.S
irq_ca.S   -> irq_armv7a.S
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@RobertRostohar
RobertRostohar committed May 14, 2021
1 parent 2929d74 commit 95fe964
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Showing 15 changed files with 215 additions and 581 deletions.
50 changes: 25 additions & 25 deletions ARM.CMSIS.pdsc
View file
Expand Up @@ -3128,13 +3128,13 @@ and 8-bit Java bytecodes in Jazelle state.
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX sources (handlers ARMCC) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s" condition="CM0_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s" condition="CM1_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s" condition="CM3_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s" condition="CM4_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s" condition="CM4_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s" condition="CM7_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s" condition="CM7_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="CM0_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="CM1_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM3_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM4_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM4_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM7_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="CM7_FP_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s" condition="CM23_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM33_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="CM33_FP_ARMCC"/>
Expand All @@ -3147,13 +3147,13 @@ and 8-bit Java bytecodes in Jazelle state.
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_ARMCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s" condition="ARMv8MML_FP_ARMCC"/>
<!-- RTX sources (handlers GCC) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S" condition="CM0_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S" condition="CM1_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S" condition="CM3_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S" condition="CM4_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S" condition="CM4_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S" condition="CM7_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S" condition="CM7_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM0_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="CM1_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM3_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM4_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="CM7_FP_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="CM23_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="CM33_FP_GCC"/>
Expand All @@ -3166,13 +3166,13 @@ and 8-bit Java bytecodes in Jazelle state.
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="ARMv8MML_FP_GCC"/>
<!-- RTX sources (handlers IAR) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s" condition="CM0_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s" condition="CM1_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s" condition="CM3_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s" condition="CM4_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s" condition="CM4_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s" condition="CM7_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s" condition="CM7_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="CM0_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="CM1_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM3_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM4_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM4_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM7_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="CM7_FP_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="CM23_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="CM33_FP_IAR"/>
Expand Down Expand Up @@ -3237,12 +3237,12 @@ and 8-bit Java bytecodes in Jazelle state.
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX sources (handlers ARMCC) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s" condition="CA_ARMCC5"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S" condition="CA_ARMCC6"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s" condition="CA_ARMCC5"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="CA_ARMCC6"/>
<!-- RTX sources (handlers GCC) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S" condition="CA_GCC"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="CA_GCC"/>
<!-- RTX sources (handlers IAR) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s" condition="CA_IAR"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s" condition="CA_IAR"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.3" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
Expand Down
11 changes: 5 additions & 6 deletions CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
View file
Expand Up @@ -1272,9 +1272,9 @@ System Control Block (SBC) | To control and setup the processor exceptions inclu
Interrupt Control | The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.

The RTX implements interfaces to the processor hardware in following files:
- <b>%irq_cm0.s</b> defines exception handlers for Cortex-M0/M0+
- <b>%irq_armv6m.s</b> defines exception handlers for Cortex-M0/M0+
\if ARMv8M
- <b>%irq_armv8mbl_common.s</b> defines exception handlers for Cortex-M23
- <b>%irq_armv8mbl.s</b> defines exception handlers for Cortex-M23
\endif
- <b>%rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- <b>%os_tick.h</b> is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.
Expand All @@ -1300,10 +1300,9 @@ NVIC Interface | CMSIS-Core function \b NVIC_GetPriorityGrouping is
LDREX, STREX instructions | Exclusive access instructions \b LDREX and \b STREX are used to implement atomic execution without disabling interrupts.

The interface files to the processor hardware are:
- <b>%irq_cm3.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.
- <b>%irq_cm4f.s</b> defines exception handlers for Cortex-M4/M7 with floating point unit.
- <b>%irq_armv7m.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7.
\if ARMv8M
- <b>%irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33/M35P
- <b>%irq_armv8mml.s</b> defines exception handlers for Cortex-M33/M35P
\endif
- <b>%rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- <b>%os_tick.h</b> is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.
Expand All @@ -1323,7 +1322,7 @@ LDREX, STREX instruction | Atomic execution avoids the requirement to disable
Interrupt Controller | An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in %irq_ctrl_gic.c using the <a class="el" href="../../Core_A/html/group__irq__ctrl__gr.html">IRQ Controller API</a>.

The interface files to the processor hardware are:
- <b>%irq_ca.s</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
- <b>%irq_armv7a.s</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
- <b>%rtx_core_ca.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- <b>%os_tick.h</b> is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the timer peripheral.
- <b>%irq_ctrl.h</b> is the <a class="el" href="../../Core_A/html/group__irq__ctrl__gr.html">IRQ Controller API</a> that defines the interface functions to the interrupt controller.
Expand Down
1 change: 1 addition & 0 deletions CMSIS/DoxyGen/RTOS2/src/history.txt
View file
Expand Up @@ -103,6 +103,7 @@
<td>
- CVE-2021-27431 vulnerability mitigation.
- Added OS Initialization for IAR.
- Reorganized IRQ module names.
</td>
</tr>
<tr>
Expand Down
24 changes: 12 additions & 12 deletions CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s → CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
View file
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -18,7 +18,7 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-M0 Exception handlers
; * Title: ARMv6-M Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
Expand All @@ -44,9 +44,9 @@ SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
ENDIF

MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
Expand All @@ -57,7 +57,7 @@ SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0

PUSH {R0,LR} ; Save SP and EXC_RETURN
Expand All @@ -68,7 +68,7 @@ SVC_Number
MOV LR,R3 ; Set EXC_RETURN

SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
Expand All @@ -78,7 +78,7 @@ SVC_Context

SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
Expand All @@ -91,12 +91,12 @@ SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next

IF :DEF:MPU_LOAD
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
ENDIF

SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
Expand All @@ -110,7 +110,7 @@ SVC_ContextRestore
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7

MOVS R0,#~0xFFFFFFFD
MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler

Expand Down Expand Up @@ -151,7 +151,7 @@ PendSV_Handler PROC
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context
B SVC_Context ; Branch to context handling

ALIGN
ENDP
Expand All @@ -165,7 +165,7 @@ SysTick_Handler PROC
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context
B SVC_Context ; Branch to context handling

ALIGN
ENDP
Expand Down
18 changes: 9 additions & 9 deletions CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s → CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
View file
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -18,7 +18,7 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-A Exception handlers
; * Title: ARMv7-A Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
Expand Down Expand Up @@ -367,16 +367,16 @@ osRtxContextSave
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment

VSTMDB R1!, {D0-D15} ; Save D0-D15
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VSTMDB R1!, {D16-D31} ; Save D16-D31
ENDIF
ENDIF

LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
ORR R2, R2, #4 ; NEON state
ELSE
ELSE
ORR R2, R2, #2 ; VFP state
ENDIF
ENDIF
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state

osRtxContextSave1
Expand Down Expand Up @@ -428,9 +428,9 @@ osRtxContextRestore
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VLDMIA LR!, {D16-D31} ; Restore D16-D31
ENDIF
ENDIF
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
Expand Down

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