Add Alpha support for SME2.1 #309

rsandifo-arm · 2024-03-08T18:31:08Z

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rsandifo-arm · 2024-03-08T18:31:39Z

This will need rebasing once SVE2.1 goes in, but I thought it was worth posting now for comments.

CarolineConcatto · 2024-04-02T10:57:17Z

main/acle.md

+Move and zero ZA tile slice to vector register.
+
+```
+  // And similarly for u8.


Should we also have :
svreadz_ver

According to the specification in ARM-software/acle#309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

… single According to the specification in ARM-software/acle#309 this adds the intrinsics // And similarly for u8. svint8_t svreadz_hor_za8_s8(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // And similarly for u16, bf16 and f16. svint16_t svreadz_hor_za16_s16(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // And similarly for u32 and f32. svint32_t svreadz_hor_za32_s32(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // And similarly for u64 and f64. svint64_t svreadz_hor_za64_s64(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // And similarly for s16, s32, s64, u8, u16, u32, u64, bf16, f16, f32, f64 svint8_t svreadz_hor_za128_s8(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za");

According to the specification in ARM-software/acle#309 this adds the intrinsics // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x2_t svreadz_hor_za8_s8_vg2(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x4_t svreadz_hor_za8_s8_vg4(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x2_t svreadz_ver_za8_s8_vg2(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x4_t svreadz_ver_za8_s8_vg4(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za");

CarolineConcatto · 2024-04-15T14:15:03Z

main/acle.md


 ``` c
+  // Variants are also available for:
+  //   _za16[_bf16]_m (only if __ARM_FEATURE_SME_B16B16 != 0)
+  //   _za16[_f16]_m (only if __ARM_FEATURE_SME_F16F16 != 0)


I notice that the instructions under ARM_FEATURE_SME_F16F16 in the ACLE
are only under FEATURE_SME_F16F16 in developer.arm(It looks like they do not require SME2),

FMLA ZA.H[[], []{, VGx2}], { [].H-[].H }, [].H[[]]
if !IsFeatureImplemented(FEAT_SME_F16F16) then UNDEFINED;
I am not sure if the ACLE should follow that or not.

momchil-velikov · 2024-04-16T09:34:38Z

main/acle.md

@@ -1948,6 +1968,20 @@ See [Half-precision brain
 floating-point](#half-precision-brain-floating-point) for details
 of half-precision brain floating-point types.

+#### Non-widening brain 16-bit floating-point support


In the Arm ARM March 2024, the feature name is FEAT_SVE_B16B16, which implies FEAT_SME2 or FEAT_SVE2. Differences with the proposed spec are:

spelling of the feature name

it does not imply SVE2.1 or SME2.1 as the text seems to suggest

Perhaps two separate macros are not needed and equivalent functionality can be obtained by, e.g.

#if defined (__ARM_FEATURE_SME) && defined (__ARM_FEATURE_SVE_B16B16) ...

momchil-velikov · 2024-04-16T09:36:20Z

main/acle.md

+extended in the future.
+
+`__ARM_FEATURE_SME_F16F16` is defined to `1` if there is hardware support
+for the SME2.1 half-precision (FEAT_SME_F16F16) instructions and if their


Only SME2 is implied by FEAT_SME_F16F16

According to the specification in ARM-software/acle#309 this adds the intrinsics Move and zero multiple ZA single-vector groups to vector registers // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x2_t svreadz_za8_s8_vg1x2(uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x4_t svreadz_za8_s8_vg1x4(uint32_t slice) __arm_streaming __arm_inout("za");

Lukacma · 2024-04-18T14:08:57Z

main/acle.md

@@ -10132,6 +10184,9 @@ Multi-vector convert to/from floating-point.

  // Variants are also available for _f32[_u32_x4], _s32[_f32_x4] and _u32[_f32_x4]
  svfloat32x4_t svcvt_f32[_s32_x4](svint32x4_t zn) __arm_streaming;
+
+  // Only if __ARM_FEATURE_SME_F16F16 != 0
+  svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming;


Wouldn't naming this svcvt_f32[_x2_f16] be more consistent as it is output that has 2 vectors ?

CarolineConcatto · 2024-04-29T09:36:11Z

main/acle.md

+  //   _single_u8_x2,
+  //   _single_bf16_x2 (only if __ARM_FEATURE_SME_B16B16)
+  //   _single_s16_x2
+  //   _single_u16_x2


According to the specification in ARM-software/acle#309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

…tors (#88266) According to the specification in ARM-software/acle#309 this adds the intrinsics void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

…tors (llvm#88266) According to the specification in ARM-software/acle#309 this adds the intrinsics void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

According to the specification in ARM-software/acle#309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

According to the specification in ARM-software/acle#309 add the following intrinsics void svmla[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmla[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmla_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmla_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmls_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmls_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmla_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmla_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) as well as the corresponding `_bf16` variants.

According to the specification in ARM-software/acle#309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

…tors (llvm#88266) According to the specification in ARM-software/acle#309 this adds the intrinsics void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

According to specifications in [ARM-software/acle/pull/309](ARM-software/acle#309) Add following intrinsics: ``` // svmax single,multi svbfloat16x2_t svmax_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm) svbfloat16x4_t svmax_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm) svbfloat16x2_t svmax_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm) svbfloat16x4_t svmax_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm) ``` ``` // svmin single,multi svbfloat16x2_t svmin_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm) svbfloat16x4_t svmin_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm) svbfloat16x2_t svmin_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm) svbfloat16x4_t svmin_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm) ``` ``` // svmaxnm single,multi svbfloat16x2_t svmaxnm_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm) svbfloat16x4_t svmaxnm_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm) svbfloat16x2_t svmaxnm_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm) svbfloat16x4_t svmaxnm_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm) ``` ``` // svminnm single,multi svbfloat16x2_t svminnm_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm) svbfloat16x4_t svminnm_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm) svbfloat16x2_t svminnm_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm) svbfloat16x4_t svminnm_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm) ``` - Variations other than bfloat16 are already supported.

…tors (#91606) [Recommit of e88ba6d] According to the specification in ARM-software/acle#309 this adds the intrinsics void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants.

According to the specification in ARM-software/acle#309 this adds the intrinsics ``` svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming; svfloat32x2_t svcvtl_f32[_f16_x2](svfloat16_t zn) __arm_streaming; ``` These are available only if __ARM_FEATURE_SME_F16F16 is enabled. --------- Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

According to the specification in ARM-software/acle#309 this adds the intrinsics: ``` void svzero_za64_vg1x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg1x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x4(uint32_t slice) __arm_streaming __arm_inout("za"); ```

According to the specification in ARM-software/acle#309 this adds the intrinsics ``` svbfloat16x2_t svclamp[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming; svbfloat16x4_t svclamp[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming; ``` These are available only if __ARM_FEATURE_SME_B16B16 is enabled.

According to the specification in ARM-software/acle#309 this adds the intrinsics ``` svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming; svfloat32x2_t svcvtl_f32[_f16_x2](svfloat16_t zn) __arm_streaming; ``` These are available only if __ARM_FEATURE_SME_F16F16 is enabled. --------- Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

According to the specification in ARM-software/acle#309 this adds the intrinsics: void svzero_za64_vg1x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg1x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x4(uint32_t slice) __arm_streaming __arm_inout("za");

According to the specification in ARM-software/acle#309 this adds the intrinsics ``` svbfloat16x2_t svclamp[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming; svbfloat16x4_t svclamp[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming; ``` These are available only if __ARM_FEATURE_SME_B16B16 is enabled.

According to the specification in ARM-software/acle#309 this adds the intrinsics ``` svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming; svfloat32x2_t svcvtl_f32[_f16_x2](svfloat16_t zn) __arm_streaming; ``` These are available only if __ARM_FEATURE_SME_F16F16 is enabled. --------- Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

According to the specification in ARM-software/acle#309 this adds the intrinsics: void svzero_za64_vg1x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg1x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg2x4(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x1(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x2(uint32_t slice) __arm_streaming __arm_inout("za"); void svzero_za64_vg4x4(uint32_t slice) __arm_streaming __arm_inout("za");

According to the specification in ARM-software/acle#309 this adds the intrinsics // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x2_t svreadz_hor_za8_s8_vg2(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x4_t svreadz_hor_za8_s8_vg4(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x2_t svreadz_ver_za8_s8_vg2(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za"); // Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and _za64_f64 svint8x4_t svreadz_ver_za8_s8_vg4(uint64_t tile, uint32_t slice) __arm_streaming __arm_inout("za");

Add Alpha support for SME2.1

57acd04

rsandifo-arm added the proposal label Mar 8, 2024

CarolineConcatto reviewed Apr 2, 2024

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momchil-velikov mentioned this pull request Apr 9, 2024

[AArch64] Add intrinsics for non-widening FMOPA/FMOPS llvm/llvm-project#88105

Merged

This was referenced Apr 9, 2024

[AArch64][SME] Add intrinsics for vector groups ZERO llvm/llvm-project#88114

Merged

[AArch64][SME] Add intrinsics for multi-vector BFCLAMP llvm/llvm-project#88251

Merged

momchil-velikov mentioned this pull request Apr 10, 2024

[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators llvm/llvm-project#88266

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CarolineConcatto mentioned this pull request Apr 12, 2024

[CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ tile to vector,… llvm/llvm-project#88499

Open

momchil-velikov mentioned this pull request Apr 15, 2024

[AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS llvm/llvm-project#88553

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CarolineConcatto mentioned this pull request Apr 15, 2024

[CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors llvm/llvm-project#88710

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CarolineConcatto reviewed Apr 15, 2024

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momchil-velikov reviewed Apr 16, 2024

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CarolineConcatto mentioned this pull request Apr 16, 2024

[CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ array to vector llvm/llvm-project#88901

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Lukacma reviewed Apr 18, 2024

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hassnaaHamdi mentioned this pull request Apr 25, 2024

[AArch64] Add intrinsics for bfloat16 min/max/minnm/maxnm llvm/llvm-project#90105

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Lukacma mentioned this pull request Apr 26, 2024

[SME] Add intrinsics for FCVT(wid.) and FCVTL llvm/llvm-project#90215

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CarolineConcatto reviewed Apr 29, 2024

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momchil-velikov mentioned this pull request May 9, 2024

[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators llvm/llvm-project#91606

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This was referenced May 23, 2024

[AArch64][SME] Add intrinsics for vector groups ZERO llvm/llvm-project#93201

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[SME] Add intrinsics for FCVT(wid.) and FCVTL llvm/llvm-project#93202

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Lukacma mentioned this pull request May 28, 2024

[AArch64][SME] Add intrinsics for multi-vector BFCLAMP llvm/llvm-project#93532

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Add Alpha support for SME2.1 #309

Add Alpha support for SME2.1 #309

rsandifo-arm commented Mar 8, 2024

rsandifo-arm commented Mar 8, 2024

CarolineConcatto Apr 2, 2024

CarolineConcatto Apr 15, 2024

momchil-velikov Apr 16, 2024

momchil-velikov Apr 16, 2024

Lukacma Apr 18, 2024 •

edited

CarolineConcatto Apr 29, 2024

Add Alpha support for SME2.1 #309

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Add Alpha support for SME2.1 #309

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rsandifo-arm commented Mar 8, 2024

rsandifo-arm commented Mar 8, 2024

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Lukacma Apr 18, 2024 • edited

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Lukacma Apr 18, 2024 •

edited