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feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated. This patch adds the initial platform support for AST2700 and also updates the documents. Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3 Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
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Aspeed AST2700 | ||
============== | ||
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Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated. | ||
Each core operates at 1.6GHz. | ||
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Boot Flow | ||
--------- | ||
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BootRom --> BL1/BL2 --> TF-A BL31 --> BL32 (optional) --> BL33 --> Linux Kernel | ||
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How to build | ||
------------ | ||
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.. code:: shell | ||
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 |
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@@ -8,6 +8,7 @@ Platform Ports | |
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allwinner | ||
arm/index | ||
ast2700 | ||
meson-axg | ||
meson-gxbb | ||
meson-gxl | ||
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/* | ||
* Copyright (c) 2023, Aspeed Technology Inc. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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#ifndef PLAT_MACROS_S | ||
#define PLAT_MACROS_S | ||
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/* --------------------------------------------- | ||
* The below required platform porting macro | ||
* prints out relevant platform registers | ||
* whenever an unhandled exception is taken in | ||
* BL31. | ||
* Clobbers: x0 - x10, x16, x17, sp | ||
* --------------------------------------------- | ||
*/ | ||
.macro plat_crash_print_regs | ||
.endm | ||
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#endif /* PLAT_MACROS_S */ |
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/* | ||
* Copyright (c) 2023, Aspeed Technology Inc. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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#ifndef PLATFORM_DEF_H | ||
#define PLATFORM_DEF_H | ||
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#include <arch.h> | ||
#include <plat/common/common_def.h> | ||
#include <platform_reg.h> | ||
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#define PLATFORM_STACK_SIZE UL(0x1000) | ||
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/* cpu topology */ | ||
#define PLATFORM_SYSTEM_COUNT U(1) | ||
#define PLATFORM_CLUSTER_COUNT U(1) | ||
#define PLATFORM_CORE_PRIMARY U(0) | ||
#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) | ||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ | ||
PLATFORM_CORE_COUNT_PER_CLUSTER) | ||
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/* arch timer */ | ||
#define PLAT_SYSCNT_CLKIN_HZ U(1600000000) | ||
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/* power domain */ | ||
#define PLAT_MAX_PWR_LVL U(1) | ||
#define PLAT_NUM_PWR_DOMAINS U(5) | ||
#define PLAT_MAX_RET_STATE U(1) | ||
#define PLAT_MAX_OFF_STATE U(2) | ||
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/* cache line size */ | ||
#define CACHE_WRITEBACK_SHIFT U(6) | ||
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) | ||
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/* translation tables */ | ||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) | ||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) | ||
#define MAX_XLAT_TABLES U(8) | ||
#define MAX_MMAP_REGIONS U(32) | ||
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/* BL31 region */ | ||
#define BL31_BASE ULL(0x400000000) | ||
#define BL31_SIZE ULL(0x400000) | ||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE) | ||
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/* BL32 region */ | ||
#define BL32_BASE BL31_LIMIT | ||
#define BL32_SIZE ULL(0x400000) | ||
#define BL32_LIMIT (BL32_BASE + BL32_SIZE) | ||
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/* console */ | ||
#define CONSOLE_UART_BASE UART12_BASE | ||
#define CONSOLE_UART_CLKIN_HZ U(1846153) | ||
#define CONSOLE_UART_BAUDRATE U(115200) | ||
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#endif /* PLATFORM_DEF_H */ |
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/* | ||
* Copyright (c) 2023, Aspeed Technology Inc. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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#ifndef PLATFORM_REG_H | ||
#define PLATFORM_REG_H | ||
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/* GIC */ | ||
#define GICD_BASE U(0x12200000) | ||
#define GICD_SIZE U(0x10000) | ||
#define GICR_BASE U(0x12280000) | ||
#define GICR_SIZE U(0x100000) | ||
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/* UART */ | ||
#define UART_BASE U(0x14c33000) | ||
#define UART12_BASE (UART_BASE + 0xb00) | ||
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/* CPU-die SCU */ | ||
#define SCU_CPU_BASE U(0x12c02000) | ||
#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) | ||
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) | ||
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) | ||
#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) | ||
#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) | ||
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#endif /* PLATFORM_REG_H */ |
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/* | ||
* Copyright (c) 2023, Aspeed Technology Inc. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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#include <arch.h> | ||
#include <common/debug.h> | ||
#include <common/desc_image_load.h> | ||
#include <drivers/arm/gicv3.h> | ||
#include <drivers/console.h> | ||
#include <drivers/ti/uart/uart_16550.h> | ||
#include <lib/xlat_tables/xlat_tables_v2.h> | ||
#include <plat/common/platform.h> | ||
#include <platform_def.h> | ||
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static console_t console; | ||
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static entry_point_info_t bl32_ep_info; | ||
static entry_point_info_t bl33_ep_info; | ||
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; | ||
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static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr) | ||
{ | ||
/* to workaround the return type mismatch */ | ||
return plat_core_pos_by_mpidr(mpidr); | ||
} | ||
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static const gicv3_driver_data_t plat_gic_data = { | ||
.gicd_base = GICD_BASE, | ||
.gicr_base = GICR_BASE, | ||
.rdistif_num = PLATFORM_CORE_COUNT, | ||
.rdistif_base_addrs = rdistif_base_addrs, | ||
.mpidr_to_core_pos = plat_mpidr_to_core_pos, | ||
}; | ||
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static const mmap_region_t plat_mmap[] = { | ||
MAP_REGION_FLAT(GICD_BASE, GICD_SIZE, | ||
MT_DEVICE | MT_RW | MT_SECURE), | ||
MAP_REGION_FLAT(GICR_BASE, GICR_SIZE, | ||
MT_DEVICE | MT_RW | MT_SECURE), | ||
MAP_REGION_FLAT(UART_BASE, PAGE_SIZE, | ||
MT_DEVICE | MT_RW | MT_SECURE), | ||
MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE, | ||
MT_DEVICE | MT_RW | MT_SECURE), | ||
{ 0 } | ||
}; | ||
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, | ||
u_register_t arg2, u_register_t arg3) | ||
{ | ||
console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ, | ||
CONSOLE_UART_BAUDRATE, &console); | ||
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console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); | ||
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bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); | ||
} | ||
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void bl31_plat_arch_setup(void) | ||
{ | ||
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, | ||
BL_CODE_END - BL_CODE_BASE, | ||
MT_CODE | MT_SECURE); | ||
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mmap_add_region(BL_CODE_END, BL_CODE_END, | ||
BL_END - BL_CODE_END, | ||
MT_RW_DATA | MT_SECURE); | ||
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mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, | ||
MT_MEMORY | MT_RW); | ||
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mmap_add(plat_mmap); | ||
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init_xlat_tables(); | ||
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enable_mmu_el3(0); | ||
} | ||
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void bl31_platform_setup(void) | ||
{ | ||
gicv3_driver_init(&plat_gic_data); | ||
gicv3_distif_init(); | ||
gicv3_rdistif_init(plat_my_core_pos()); | ||
gicv3_cpuif_enable(plat_my_core_pos()); | ||
} | ||
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) | ||
{ | ||
entry_point_info_t *ep_info; | ||
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ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; | ||
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if (!ep_info->pc) { | ||
return NULL; | ||
} | ||
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return ep_info; | ||
} |
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/* | ||
* Copyright (c) 2023, Aspeed Technology Inc. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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#include <asm_macros.S> | ||
#include <assert_macros.S> | ||
#include <arch.h> | ||
#include <cortex_a35.h> | ||
#include <platform_def.h> | ||
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.globl plat_is_my_cpu_primary | ||
.globl plat_my_core_pos | ||
.globl plat_secondary_cold_boot_setup | ||
.globl plat_get_syscnt_freq2 | ||
.globl plat_crash_console_init | ||
.globl plat_crash_console_putc | ||
.globl plat_crash_console_flush | ||
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/* unsigned int plat_is_my_cpu_primary(void); */ | ||
func plat_is_my_cpu_primary | ||
mrs x0, mpidr_el1 | ||
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) | ||
cmp x0, #PLATFORM_CORE_PRIMARY | ||
cset w0, eq | ||
ret | ||
endfunc plat_is_my_cpu_primary | ||
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/* unsigned int plat_my_core_pos(void); */ | ||
func plat_my_core_pos | ||
mrs x0, mpidr_el1 | ||
mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER | ||
and x1, x0, #MPIDR_CPU_MASK | ||
and x0, x0, #MPIDR_CLUSTER_MASK | ||
madd x0, x0, x2, x1 | ||
ret | ||
endfunc plat_my_core_pos | ||
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/* unsigned int plat_get_syscnt_freq2(void); */ | ||
func plat_get_syscnt_freq2 | ||
mov_imm w0, PLAT_SYSCNT_CLKIN_HZ | ||
ret | ||
endfunc plat_get_syscnt_freq2 | ||
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/* int plat_crash_console_init(void); */ | ||
func plat_crash_console_init | ||
mov_imm x0, CONSOLE_UART_BASE | ||
mov_imm x1, CONSOLE_UART_CLKIN_HZ | ||
mov_imm x2, CONSOLE_UART_BAUDRATE | ||
b console_16550_core_init | ||
endfunc plat_crash_console_init | ||
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/* int plat_crash_console_putc(int); */ | ||
func plat_crash_console_putc | ||
mov_imm x1, CONSOLE_UART_BASE | ||
b console_16550_core_putc | ||
endfunc plat_crash_console_putc | ||
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/* void plat_crash_console_flush(void); */ | ||
func plat_crash_console_flush | ||
mov_imm x0, CONSOLE_UART_BASE | ||
b console_16550_core_flush | ||
endfunc plat_crash_console_flush |
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