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bl1_arch_setup() should not program the counter frequency #24

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danh-arm opened this issue Feb 5, 2014 · 0 comments
Closed

bl1_arch_setup() should not program the counter frequency #24

danh-arm opened this issue Feb 5, 2014 · 0 comments
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@danh-arm
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danh-arm commented Feb 5, 2014

Currently bl1_arch_setup() programs the counter frequency:

    /* Read the frequency from Frequency modes table */
    counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE +
    CNTFID_OFF);
    /* The first entry of the frequency modes table must not be 0 */
    assert(counter_base_frequency != 0);

    /* Program the counter frequency */
    write_cntfrq_el0(counter_base_frequency);

Not all platforms have a memory mapped timer and not all platforms will have initialized this by the time BL1 starts (causing the assert to fail). Also, bl31_arch_setup() does the same thing later.

This code should be removed from bl1_arch_setup() and the equivalent code in bl31_arch_setup() should be moved to bl31_platform_setup().

In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time.

@jeenuv jeenuv self-assigned this Mar 6, 2014
sandrine-bailleux-arm added a commit to sandrine-bailleux-arm/arm-trusted-firmware that referenced this issue Apr 8, 2014
BL3-1 architecture setup code programs the system counter frequency
into the CNTFRQ_EL0 register. This frequency is defined by the
platform, though. This patch introduces a new platform hook that
the architecture setup code can call to retrieve this information.
In the ARM FVP port, this returns the first entry of the frequency
modes table from the memory mapped generic timer.

All system counter setup code has been removed from BL1 as some
platforms may not have initialized the system counters at this stage.
The platform specific settings done exclusively in BL1 have been moved
to BL3-1. In the ARM FVP port, this consists in enabling and
initializing the System level generic timer. Also, the frequency change
request in the counter control register has been set to 0 to make it
explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
fixed in this context to give an entry number rather than a bitmask.

In future, when support for firmware update is implemented, there
is a case where BL1 platform specific code will need to program
the counter frequency. This should be implemented at that time.

This patch also updates the relevant documentation.

It properly fixes ARM-software/tf-issues#24

Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
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