[HAL LPC43xx] Fix mask bits for SPI clock rate

ARMmbed · Aug 9, 2017 · da7fa0d · da7fa0d
1 parent 72e8241
commit da7fa0d
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c
@@ -117,7 +117,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
 
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -152,7 +152,7 @@ void spi_frequency(spi_t *obj, int hz) {
             obj->spi->CPSR = prescaler;
 
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;