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Merge pull request #5824 from jeromecoutant/DEV_DISCO_F407
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DISCO_F407VG : alignment with other STM32
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@0xc0170
0xc0170 committed Jan 15, 2018
2 parents 8c78649 + 0eede79 commit debca1f
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Showing 5 changed files with 715 additions and 35 deletions.
14 changes: 7 additions & 7 deletions targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h
View file
Expand Up @@ -197,13 +197,13 @@ typedef enum {
ADC_VBAT = 0xF2,

// Generic signals namings
LED1 = PD_13,
LED2 = PD_12,
LED3 = PD_13,
LED4 = PD_12,
LED5 = PD_14,
LED6 = PD_15,
LED_RED = LED1,
LED1 = PD_13, // LD3 as LD1 is not a user LED
LED2 = PD_12, // LD4 as LD2 is not a user LED
LED3 = PD_13, // orange
LED4 = PD_12, // green
LED5 = PD_14, // red
LED6 = PD_15, // blue
LED_RED = LED5,
USER_BUTTON = PA_0,
// Standardized button names
BUTTON1 = USER_BUTTON,
Expand Down
58 changes: 31 additions & 27 deletions targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c
View file
Expand Up @@ -17,25 +17,20 @@
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 16 MHz)
* | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
* | 3- USE_PLL_HSI (internal 16 MHz)
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 168 | 168
*-----------------------------------------------------------------------------
* AHBCLK (MHz) | 168 | 168
*-----------------------------------------------------------------------------
* APB1CLK (MHz) | 42 | 42
*-----------------------------------------------------------------------------
* APB2CLK (MHz) | 84 | 84
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | NO
* SYSCLK(MHz) | 168
* AHBCLK (MHz) | 168
* APB1CLK (MHz) | 42
* APB2CLK (MHz) | 84
* USB capable | YES
*-----------------------------------------------------------------------------
**/

#include "stm32f4xx.h"

#include "mbed_assert.h"

/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
Expand All @@ -44,16 +39,20 @@
This value must be a multiple of 0x200. */


/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
#define USE_PLL_HSI 0x2 // Use HSI internal clock


#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

#if ((CLOCK_SOURCE) & USE_PLL_HSI)
uint8_t SetSysClock_PLL_HSI(void);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */


/**
* @brief Setup the microcontroller system
Expand Down Expand Up @@ -110,20 +109,23 @@ void SystemInit(void)
*/
void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
#if USE_PLL_HSE_EXTC != 0
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
#if USE_PLL_HSE_XTAL != 0
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0) {
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
// [TODO] Put something here to tell the user that a problem occured...
MBED_ASSERT(1);
}
}
}
Expand All @@ -133,14 +135,14 @@ void SetSysClock(void)
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
}

#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;

/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
Expand Down Expand Up @@ -186,15 +188,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)

return 1; // OK
}
#endif
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;

/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
Expand Down Expand Up @@ -232,3 +235,4 @@ uint8_t SetSysClock_PLL_HSI(void)

return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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