SPI FPGA test extension + SPI driver fix (K64F) #10989
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fkjagodzinski
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Jul 8, 2019
0xc0170
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Jul 8, 2019
| spi_init(&spi, mosi, miso, sclk, ssel); | ||
| spi_format(&spi, sym_size, spi_mode, 0); | ||
| spi_frequency(&spi, 1000000); | ||
| spi_frequency(&spi, freqency); |
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there are same typo in bellow code as well
Add test cases for: - async mode, - different frequencies, - block write
FPGA test shield requires at lease half slck period delay between CS assertion and first sclk edge.
Co-Authored-By: Filip Jagodziński <fkjagodzinski@gmail.com>
ciarmcom
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0xc0170,
fkjagodzinski,
jamesbeyond,
maciejbocianski,
maclobdell and
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@mprse, thank you for your changes. |
c1728p9
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Jul 8, 2019
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jamesbeyond
approved these changes
Jul 8, 2019
0xc0170
approved these changes
Jul 8, 2019
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CI started |
fkjagodzinski
approved these changes
Jul 8, 2019
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
|
@0xc0170 This one i ready to go in. |
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Description
This PR:
This PR requires first: PR #10975
Pull request type
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@jamesbeyond @0xc0170 @fkjagodzinski @maciejbocianski