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Increase ADC tolerance to 5% in FPGA-based tests #11014
Increase ADC tolerance to 5% in FPGA-based tests #11014
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@stevew817, thank you for your changes. |
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Can you add this to the commit msg:
During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results
During the SiP workshop, we discovered that 3% is too narrow due to a combination of: Voltage rail differences between target and FPGA Extension of lesser-resolution ADC's to 16-bit results
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@0xc0170 Done. |
CI started |
Test run: FAILEDSummary: 1 of 4 test jobs failed Failed test jobs:
|
Looks like a CI problem, CI restarted. |
Test run: SUCCESSSummary: 4 of 4 test jobs passed |
Description
During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Pull request type
Reviewers
@c1728p9
Release Notes