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Increase ADC tolerance to 5% in FPGA-based tests #11014

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stevew817
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Description

During the SiP workshop, we discovered that 3% is too narrow due to a combination of:

  • Voltage rail differences between target and FPGA
  • Extension of lesser-resolution ADC's to 16-bit results

Pull request type

[ ] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[X] Test update
[ ] Breaking change

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@c1728p9

Release Notes

@ciarmcom ciarmcom requested review from c1728p9 and a team July 10, 2019 11:00
@ciarmcom
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@stevew817, thank you for your changes.
@c1728p9 @ARMmbed/mbed-os-hal @ARMmbed/mbed-os-test @ARMmbed/mbed-os-maintainers please review.

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@0xc0170 0xc0170 left a comment

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Can you add this to the commit msg:

During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results

During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results
@stevew817 stevew817 force-pushed the fix/fpga_tests/adc_methodology branch from f1cdb98 to f6a70b2 Compare July 10, 2019 13:13
@stevew817
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@0xc0170 Done.

@evedon
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evedon commented Jul 12, 2019

CI started

@mbed-ci
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mbed-ci commented Jul 12, 2019

Test run: FAILED

Summary: 1 of 4 test jobs failed
Build number : 1
Build artifacts

Failed test jobs:

  • jenkins-ci/mbed-os-ci_greentea-test

@artokin
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artokin commented Jul 15, 2019

Looks like a CI problem, CI restarted.

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mbed-ci commented Jul 15, 2019

Test run: SUCCESS

Summary: 4 of 4 test jobs passed
Build number : 2
Build artifacts

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9 participants