-
Notifications
You must be signed in to change notification settings - Fork 3k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
STM32 SPI ASYNC - Add FIFO flush before transfer #6012
Conversation
ST_INTERNAL_REF 43358
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Any tests run (ci shield for instance?) ?
Yes, SPI tests have been performed with CI shield: +-----------------------+---------------+-----------------------+--------+--------------------+-------------+ |
/morph build |
Build : SUCCESSBuild number : 1059 Triggering tests/morph test |
Test : SUCCESSBuild number : 865 |
Exporter Build : SUCCESSBuild number : 738 |
Description
In STM32F0/F3/F7/L4, there is a FIFO that needs to be flushed before starting transfers.
NB: some HAL files were missing for STM32F7 (ST_INTERNAL_REF 43358)
Status
READY