LPC546XX, MIMXRT1050: Update to fix ARMC6 build failures

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_common.h

@@ -238,16 +238,16 @@ _Pragma("diag_suppress=Pm120")
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
 #endif
-#elif defined(__ARMCC_VERSION)
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
 /*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 /*! Macro to define a variable with L1 d-cache line size alignment */
 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
 #endif
 /*! Macro to define a variable with L2 cache line size alignment */
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
 #endif
 #elif defined(__GNUC__)
 /*! Macro to define a variable with alignbytes alignment */
@@ -295,19 +295,19 @@ _Pragma("diag_suppress=Pm120")
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
 #endif
-#elif(defined(__ARMCC_VERSION))
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
-    __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
-    __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
 #else
 #define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #endif
 #elif(defined(__GNUC__))
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
@@ -446,10 +446,10 @@ _Pragma("diag_suppress=Pm120")
     }
 
     /*!
-     * @brief Enaable the global IRQ
+     * @brief Enable the global IRQ
      *
      * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
-     * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
      * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
      *
      * @param primask value of primask register to be restored. The primask value is supposed to be provided by the

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c

@@ -37,7 +37,7 @@
  * Code
  ******************************************************************************/
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
 __attribute__((section(".boot_hdr.conf")))
 #elif defined(__ICCARM__)
 #pragma location = ".boot_hdr.conf"

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c

@@ -35,7 +35,7 @@
 
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
 __attribute__((section(".boot_hdr.dcd_data")))
 #elif defined(__ICCARM__)
 #pragma location = ".boot_hdr.dcd_data"

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h

@@ -31,7 +31,7 @@
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
 extern uint32_t Image$$VECTOR_RAM$$Base[];
 #define __VECTOR_RAM Image$$VECTOR_RAM$$Base
 #else

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h

@@ -249,16 +249,16 @@ _Pragma("diag_suppress=Pm120")
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
 #endif
-#elif defined(__ARMCC_VERSION)
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
 /*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 /*! Macro to define a variable with L1 d-cache line size alignment */
 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
 #endif
 /*! Macro to define a variable with L2 cache line size alignment */
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
 #endif
 #elif defined(__GNUC__)
 /*! Macro to define a variable with alignbytes alignment */
@@ -306,19 +306,19 @@ _Pragma("diag_suppress=Pm120")
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
 #endif
-#elif(defined(__ARMCC_VERSION))
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
-    __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
-    __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
 #else
 #define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #endif
 #elif(defined(__GNUC__))
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
@@ -459,10 +459,10 @@ _Pragma("diag_suppress=Pm120")
     }
 
     /*!
-     * @brief Enaable the global IRQ
+     * @brief Enable the global IRQ
      *
      * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
-     * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
      * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
      *
      * @param primask value of primask register to be restored. The primask value is supposed to be provided by the

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c

@@ -34,7 +34,7 @@
 #include "fsl_flexspi_nor_boot.h"
 
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
     __attribute__((section(".boot_hdr.ivt")))
 #elif defined(__ICCARM__)
 #pragma location=".boot_hdr.ivt"
@@ -53,7 +53,7 @@ const ivt image_vector_table = {
   IVT_RSVD                            /* Reserved = 0 */
 };
 
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
     __attribute__((section(".boot_hdr.boot_data")))
 #elif defined(__ICCARM__)
 #pragma location=".boot_hdr.boot_data"

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h

@@ -83,7 +83,7 @@ typedef struct _ivt_ {
 #define IVT_HEADER           (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
 
 /* Set resume entry */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
     extern uint32_t __Vectors[];
     extern uint32_t Image$$RW_m_config_text$$Base[];
 #define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)