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Update to 2-region model for HEAP and Stack Memory #9571
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a322327
Use 2-region memory model in ARM rtos-less builds.
mprse e60a0f4
Remove duplicated _mbed_user_setup_stackheap, __rt_lib_init definitions.
mprse 9c11288
mbed_retarget.cpp: Fixed style
mprse 26a6a9a
Add RAM memory model update document
a1fe750
Interrupt stack is always explicitly specified, hence other condition…
41eaefe
Update memory model for stack and heap memory
8b02a60
TARGET_ARM_FM: Set the heap size and limit
25bceda
TARGET_Atmel: Set the heap size and limit
5e4dcab
Target_Cypress: Set the heap limit
e03455a
Target_Freescale: Set the heap size and limit
25a127e
target_Gigadevice: Set the heap size and limit
8c63dbe
Target_Maxim: Setup heap limit and size
b2e189f
Target_Nuvoton: Remove target specific implementation of _sbrk
57b9ccc
Target_NXP: Setup heap limit and size
73f4a52
Target_ONSEMI: Setup heap limit and size
a814078
Target_UNO_91H: Remove custom _sbrk, update heap limits
c85ca4d
TARGET_RENESAS: _sbrk updated to use limits from linker files no need…
1f57568
TARGET_Silicon_Labs Setup heap limit and size
e522c46
Target_STM:_sbrk updated to use limits from linker files no need to s…
72ae546
TARGET_TOSHIBA :Setup heap limit and size
c6a72f2
TARGET_TT: Setup heap limit and size
462f339
TARGET_Wiznet: Setup heap limit and size
537b364
Resolve build/type cast errors
d0cc7ac
Target_Cypress: Update linker files to add heap limit
9ed7e4d
Remove unnecessary endif
9d1ce66
ISR_STACK_START/ HEAP_START defines not used by GCC_ARM toolchain
b36147f
ISR_Stack_start/size defines are not needed, use linker file defines
f13a3e3
Fix GCC _sbrk allocation
e7e9e07
Update K64F linker files for general solution of 2-ram regions
9231e26
Corrected main thread stack size, was accidently updated by removing …
2a1211a
Add heaplimit to NRF52 devices
1a1c74c
mbed_rtx.h not to include in platform
38e9314
Add missing space in linker script
60e7a7d
Add heap section to linker file
f518a69
Remove unused heap_size define
c5ad5f6
Target_Freescale:Add heap section
0d4d45e
Spell correction in design doc
dab2a30
Target_Freescale: Add heap section in linker files
387e4ca
New heap can be equal to heap limit for last chunk
49266c1
Remove TOOLCHAIN_GCC_CW_NEWLIB files
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docs/design-documents/platform/memory-model/ram_memory_model.md
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# RAM memory model update - Mbed OS | ||
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# Table of contents | ||
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1. [RAM memory model update - Mbed OS](#mbed-os-ram-memory-model). | ||
1. [Table of contents](#table-of-contents). | ||
1. [Revision history](#revision-history). | ||
1. [Introduction](#introduction). | ||
1. [Current RAM memory model](#current-ram-memory-model). | ||
1. [Proposed RAM memory model](#proposed-ram-memory-model). | ||
1. [Phases](#phases). | ||
1. Detailed Design (#detailed-design). | ||
1. [Tools and configuration changes](#tools-and-configuration-changes). | ||
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### Revision history | ||
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1.0 - A brief description of this version. For example, Initial revision - Author name - Date. | ||
**NOTE: You may also specify the Mbed OS version this revision of design document applies to.** | ||
1.1 - Added new section - Author name - Date. | ||
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# Introduction | ||
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### Current RAM memory model | ||
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Single memory space is shared between stack and heap memory, start address is fixed but the size of both regions varies based on application and usage runtime. | ||
Heap starts at the first address after the end of ZI growing up into higher memory address and stack starts at the last memory address of RAM growing downward into lower addresses. | ||
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+----------------------+ Stack Start (Last address of RAM) | ||
| ISR stack | | ||
| Main Stack(No RTOS) | | ||
| | | | ||
| V | | ||
+----------------------+ | ||
| ^ | | ||
| | | | ||
| Heap | | ||
+----------------------+ HEAP Start | ||
| ZI | | ||
|(Idle, Timer and Main | | ||
| stack is in ZI for | | ||
| RTOS) | | ||
+----------------------+ | ||
| | | ||
+----------------------+ First address of RAM | ||
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#### Drawbacks: | ||
1. Collisions between stack and heap are hard to detect and result in hardfault. | ||
1. Cannot check stack limit - In case of new ARM architecture stack limit registers are available to verify stack boundaries, but this feature cannot be used with dynamic stack size. | ||
1. Stack size unification cannot be achieved across various targets. | ||
1. GCC ARM: Memory allocator request memory at 4K boundary end of HEAP memory should be 4K aligned. Placing ISR stack (1K) after HEAP memory in case of RTOS, results in loss of 3K RAM memory | ||
1. Memory allocators do not support HEAP split into multiple banks, hence with single region memory model HEAP is used only till end of first bank. | ||
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### Proposed RAM memory model | ||
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2-region memory model for heap and stack. Defined boundaries for ISR stack memory. Heap memory can be dynamic (starts at end of ZI and ends at last RAM address) or with fix boundaries in separate RAM bank. | ||
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+----------------------+ Heap Ends (Last address of RAM) | ||
| ^ | | ||
| | | | ||
| Heap | | ||
+----------------------+ HEAP Start | ||
| ZI | | ||
|(Idle, Timer and Main | | ||
| stack is in ZI for | | ||
| RTOS) | | ||
+----------------------+Stack Ends | ||
| ISR stack | | ||
| Main Stack(No RTOS) | | ||
| | | | ||
| V | | ||
+----------------------+Stack Start | ||
| | | ||
+----------------------+ First address of RAM | ||
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#### Drawbacks: | ||
1. ISR Stack is not dynamic - This drawback is mainly for bare metal implementation (RTOS-less) where ISR and Main stack is same. With this limitation application writer should know if stack or heap will be usued more and tweaks the values accordingly. | ||
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# Phases: | ||
This feature will be implemented in different phases as follow: | ||
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Phase 1 (5.12 Release): | ||
1. Adopt 2-region memory model for Stack and Heap memory. | ||
1. Unify the stack size accross all targets (RTOS: ISR stack - 1K Main thread Stack - 4K; Bare Metal(No RTOS) ISR/Main Stack - 4K) | ||
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Phase 2: | ||
1. Heap memory to be dynamic and starts at the end of ZI growing up till end of RAM memory (In case of single RAM bank) | ||
Heap memory to be dynamic and assigned partial or full RAM bank in case of multiple RAM banks, based on calculation of other RAM regions. | ||
1. ISR Stack to be placed after vectors or before ZI memory section. | ||
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Note: Heap split support across multiple RAM banks, can also be achieved post this change. | ||
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# Detailed Design | ||
1. Update tools to set define `MBED_BOOT_STACK_SIZE` from target config option `target.boot-stack-size` | ||
1. Linker Scripts - Update linker scripts for ARM, IAR and GCC toolchain to use MBED_BOOT_STACK_SIZE define for standardizing size of ISR stack. | ||
1. Update __user_setup_stackheap() implementation to adopt 2-region RAM memory model. | ||
__user_setup_stackheap() works with systems where the application starts with a value of sp (r13) that is already correct. To make use of sp(stack base), implement __user_setup_stackheap() to set up r0 (heap base), r2 (heap limit), and r3 (stack limit) (for a two-region model) and return. | ||
Reference http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0099a/armlib_cjagaaha.htm http://www.keil.com/support/man/docs/armlib/armlib_chr1359122863069.htm | ||
1. Modify _sbrk() implementation for GCC to use 2-region memory model | ||
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# Tools and configuration changes | ||
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1. Target config option "target.boot-stack-size" which is passed to the linker as the define "MBED_BOOT_STACK_SIZE" so the linker can adjust the stack accordingly. | ||
Boot stack size - the size of ISR and main stack will be 4K as default in targets.json for bare metal (non-RTOS) builds. | ||
Boot stack size - the size of ISR stack will be over-written as 1K in `rtos/mbed_lib.json` for RTOS builds. | ||
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so what phase is being implemented in this PR ? is it Phase 1 only ?
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Yes Phase 1 in this PR (5.12)