firbandpass.v

// -------------------------------------------------------------
// bandpass filter created using verilog code
// band-pass
// Module: basicfir
// Generated by MATLAB(R) 9.4 and Filter Design HDL Coder 3.1.3.
// Generated on: 2020-09-06 04:30:52
// Tutorial-Basic FIR filter
//
// -------------------------------------------------------------

// -------------------------------------------------------------
// HDL Code Generation Options:
//
// AddInputRegister: off
// InputPort: data_in
// OutputPort: data_out
// Name: basicfir
// UserComment:  User data, length 25
// TargetLanguage: Verilog
// TestBenchName: basifir_tb
// TestBenchStimulus: impulse step ramp chirp noise 

// -------------------------------------------------------------
// HDL Implementation    : Fully parallel
// Folding Factor        : 1
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Filter (real)
// -------------------------------
// Filter Structure  : Direct-Form FIR
// Filter Length     : 51
// Stable            : Yes
// Linear Phase      : Yes (Type 1)
// Arithmetic        : fixed
// Numerator         : s14,15 -> [-2.500000e-01 2.500000e-01)
// Input             : s8,9 -> [-2.500000e-01 2.500000e-01)
// Filter Internals  : Specify Precision
//   Output          : s8,32 -> [-2.980232e-08 2.980232e-08)
//   Product         : s16,17 -> [-2.500000e-01 2.500000e-01)
//   Accumulator     : s20,20 -> [-5.000000e-01 5.000000e-01)
//   Round Mode      : floor
//   Overflow Mode   : saturate
// -------------------------------------------------------------




`timescale 1 ns / 1 ns

module basicfir
               (
                clk,
                clk_enable,
                reset,
                data_in,
                data_out
                );

  input   clk; 
  input   clk_enable; 
  input   reset; 
  input   signed [7:0] data_in; //sfix8_En9
  output  signed [7:0] data_out; //sfix8_En32

////////////////////////////////////////////////////////////////
//Module Architecture: basicfir
////////////////////////////////////////////////////////////////
  // Local Functions
  // Type Definitions
  // Constants
  parameter signed [13:0] coeff1 = 14'b00000000001101; //sfix14_En15
  parameter signed [13:0] coeff2 = 14'b11111111110101; //sfix14_En15
  parameter signed [13:0] coeff3 = 14'b11111110100110; //sfix14_En15
  parameter signed [13:0] coeff4 = 14'b11111111000111; //sfix14_En15
  parameter signed [13:0] coeff5 = 14'b00000010101001; //sfix14_En15
  parameter signed [13:0] coeff6 = 14'b00000011010100; //sfix14_En15
  parameter signed [13:0] coeff7 = 14'b11111101000110; //sfix14_En15
  parameter signed [13:0] coeff8 = 14'b11111001100000; //sfix14_En15
  parameter signed [13:0] coeff9 = 14'b00000001010001; //sfix14_En15
  parameter signed [13:0] coeff10 = 14'b00001000001101; //sfix14_En15
  parameter signed [13:0] coeff11 = 14'b00000001001001; //sfix14_En15
  parameter signed [13:0] coeff12 = 14'b11111001100100; //sfix14_En15
  parameter signed [13:0] coeff13 = 14'b11111111010010; //sfix14_En15
  parameter signed [13:0] coeff14 = 14'b00000010000101; //sfix14_En15
  parameter signed [13:0] coeff15 = 14'b11111001100001; //sfix14_En15
  parameter signed [13:0] coeff16 = 14'b11111111111111; //sfix14_En15
  parameter signed [13:0] coeff17 = 14'b00010100111010; //sfix14_En15
  parameter signed [13:0] coeff18 = 14'b00000110110110; //sfix14_En15
  parameter signed [13:0] coeff19 = 14'b11011010111111; //sfix14_En15
  parameter signed [13:0] coeff20 = 14'b11100110001001; //sfix14_En15
  parameter signed [13:0] coeff21 = 14'b00101101001110; //sfix14_En15
  parameter signed [13:0] coeff22 = 14'b00110100111011; //sfix14_En15
  parameter signed [13:0] coeff23 = 14'b11011010001110; //sfix14_En15
  parameter signed [13:0] coeff24 = 14'b10110010111000; //sfix14_En15
  parameter signed [13:0] coeff25 = 14'b00001110110001; //sfix14_En15
  parameter signed [13:0] coeff26 = 14'b01010110110111; //sfix14_En15
  parameter signed [13:0] coeff27 = 14'b00001110110001; //sfix14_En15
  parameter signed [13:0] coeff28 = 14'b10110010111000; //sfix14_En15
  parameter signed [13:0] coeff29 = 14'b11011010001110; //sfix14_En15
  parameter signed [13:0] coeff30 = 14'b00110100111011; //sfix14_En15
  parameter signed [13:0] coeff31 = 14'b00101101001110; //sfix14_En15
  parameter signed [13:0] coeff32 = 14'b11100110001001; //sfix14_En15
  parameter signed [13:0] coeff33 = 14'b11011010111111; //sfix14_En15
  parameter signed [13:0] coeff34 = 14'b00000110110110; //sfix14_En15
  parameter signed [13:0] coeff35 = 14'b00010100111010; //sfix14_En15
  parameter signed [13:0] coeff36 = 14'b11111111111111; //sfix14_En15
  parameter signed [13:0] coeff37 = 14'b11111001100001; //sfix14_En15
  parameter signed [13:0] coeff38 = 14'b00000010000101; //sfix14_En15
  parameter signed [13:0] coeff39 = 14'b11111111010010; //sfix14_En15
  parameter signed [13:0] coeff40 = 14'b11111001100100; //sfix14_En15
  parameter signed [13:0] coeff41 = 14'b00000001001001; //sfix14_En15
  parameter signed [13:0] coeff42 = 14'b00001000001101; //sfix14_En15
  parameter signed [13:0] coeff43 = 14'b00000001010001; //sfix14_En15
  parameter signed [13:0] coeff44 = 14'b11111001100000; //sfix14_En15
  parameter signed [13:0] coeff45 = 14'b11111101000110; //sfix14_En15
  parameter signed [13:0] coeff46 = 14'b00000011010100; //sfix14_En15
  parameter signed [13:0] coeff47 = 14'b00000010101001; //sfix14_En15
  parameter signed [13:0] coeff48 = 14'b11111111000111; //sfix14_En15
  parameter signed [13:0] coeff49 = 14'b11111110100110; //sfix14_En15
  parameter signed [13:0] coeff50 = 14'b11111111110101; //sfix14_En15
  parameter signed [13:0] coeff51 = 14'b00000000001101; //sfix14_En15

  // Signals
  reg  signed [7:0] delay_pipeline [0:49] ; // sfix8_En9
  wire signed [15:0] product51; // sfix16_En17
  wire signed [21:0] mul_temp; // sfix22_En24
  wire signed [15:0] product50; // sfix16_En17
  wire signed [21:0] mul_temp_1; // sfix22_En24
  wire signed [15:0] product49; // sfix16_En17
  wire signed [21:0] mul_temp_2; // sfix22_En24
  wire signed [15:0] product48; // sfix16_En17
  wire signed [21:0] mul_temp_3; // sfix22_En24
  wire signed [15:0] product47; // sfix16_En17
  wire signed [21:0] mul_temp_4; // sfix22_En24
  wire signed [15:0] product46; // sfix16_En17
  wire signed [21:0] mul_temp_5; // sfix22_En24
  wire signed [15:0] product45; // sfix16_En17
  wire signed [21:0] mul_temp_6; // sfix22_En24
  wire signed [15:0] product44; // sfix16_En17
  wire signed [21:0] mul_temp_7; // sfix22_En24
  wire signed [15:0] product43; // sfix16_En17
  wire signed [21:0] mul_temp_8; // sfix22_En24
  wire signed [15:0] product42; // sfix16_En17
  wire signed [21:0] mul_temp_9; // sfix22_En24
  wire signed [15:0] product41; // sfix16_En17
  wire signed [21:0] mul_temp_10; // sfix22_En24
  wire signed [15:0] product40; // sfix16_En17
  wire signed [21:0] mul_temp_11; // sfix22_En24
  wire signed [15:0] product39; // sfix16_En17
  wire signed [21:0] mul_temp_12; // sfix22_En24
  wire signed [15:0] product38; // sfix16_En17
  wire signed [21:0] mul_temp_13; // sfix22_En24
  wire signed [15:0] product37; // sfix16_En17
  wire signed [21:0] mul_temp_14; // sfix22_En24
  wire signed [15:0] product36; // sfix16_En17
  wire signed [8:0] mulpwr2_temp; // sfix9_En9
  wire signed [15:0] product35; // sfix16_En17
  wire signed [21:0] mul_temp_15; // sfix22_En24
  wire signed [15:0] product34; // sfix16_En17
  wire signed [21:0] mul_temp_16; // sfix22_En24
  wire signed [15:0] product33; // sfix16_En17
  wire signed [21:0] mul_temp_17; // sfix22_En24
  wire signed [15:0] product32; // sfix16_En17
  wire signed [21:0] mul_temp_18; // sfix22_En24
  wire signed [15:0] product31; // sfix16_En17
  wire signed [21:0] mul_temp_19; // sfix22_En24
  wire signed [15:0] product30; // sfix16_En17
  wire signed [21:0] mul_temp_20; // sfix22_En24
  wire signed [15:0] product29; // sfix16_En17
  wire signed [21:0] mul_temp_21; // sfix22_En24
  wire signed [15:0] product28; // sfix16_En17
  wire signed [21:0] mul_temp_22; // sfix22_En24
  wire signed [15:0] product27; // sfix16_En17
  wire signed [21:0] mul_temp_23; // sfix22_En24
  wire signed [15:0] product26; // sfix16_En17
  wire signed [21:0] mul_temp_24; // sfix22_En24
  wire signed [15:0] product25; // sfix16_En17
  wire signed [21:0] mul_temp_25; // sfix22_En24
  wire signed [15:0] product24; // sfix16_En17
  wire signed [21:0] mul_temp_26; // sfix22_En24
  wire signed [15:0] product23; // sfix16_En17
  wire signed [21:0] mul_temp_27; // sfix22_En24
  wire signed [15:0] product22; // sfix16_En17
  wire signed [21:0] mul_temp_28; // sfix22_En24
  wire signed [15:0] product21; // sfix16_En17
  wire signed [21:0] mul_temp_29; // sfix22_En24
  wire signed [15:0] product20; // sfix16_En17
  wire signed [21:0] mul_temp_30; // sfix22_En24
  wire signed [15:0] product19; // sfix16_En17
  wire signed [21:0] mul_temp_31; // sfix22_En24
  wire signed [15:0] product18; // sfix16_En17
  wire signed [21:0] mul_temp_32; // sfix22_En24
  wire signed [15:0] product17; // sfix16_En17
  wire signed [21:0] mul_temp_33; // sfix22_En24
  wire signed [15:0] product16; // sfix16_En17
  wire signed [8:0] mulpwr2_temp_1; // sfix9_En9
  wire signed [15:0] product15; // sfix16_En17
  wire signed [21:0] mul_temp_34; // sfix22_En24
  wire signed [15:0] product14; // sfix16_En17
  wire signed [21:0] mul_temp_35; // sfix22_En24
  wire signed [15:0] product13; // sfix16_En17
  wire signed [21:0] mul_temp_36; // sfix22_En24
  wire signed [15:0] product12; // sfix16_En17
  wire signed [21:0] mul_temp_37; // sfix22_En24
  wire signed [15:0] product11; // sfix16_En17
  wire signed [21:0] mul_temp_38; // sfix22_En24
  wire signed [15:0] product10; // sfix16_En17
  wire signed [21:0] mul_temp_39; // sfix22_En24
  wire signed [15:0] product9; // sfix16_En17
  wire signed [21:0] mul_temp_40; // sfix22_En24
  wire signed [15:0] product8; // sfix16_En17
  wire signed [21:0] mul_temp_41; // sfix22_En24
  wire signed [15:0] product7; // sfix16_En17
  wire signed [21:0] mul_temp_42; // sfix22_En24
  wire signed [15:0] product6; // sfix16_En17
  wire signed [21:0] mul_temp_43; // sfix22_En24
  wire signed [15:0] product5; // sfix16_En17
  wire signed [21:0] mul_temp_44; // sfix22_En24
  wire signed [15:0] product4; // sfix16_En17
  wire signed [21:0] mul_temp_45; // sfix22_En24
  wire signed [15:0] product3; // sfix16_En17
  wire signed [21:0] mul_temp_46; // sfix22_En24
  wire signed [15:0] product2; // sfix16_En17
  wire signed [21:0] mul_temp_47; // sfix22_En24
  wire signed [19:0] product1_cast; // sfix20_En20
  wire signed [15:0] product1; // sfix16_En17
  wire signed [21:0] mul_temp_48; // sfix22_En24
  wire signed [19:0] sum1; // sfix20_En20
  wire signed [19:0] add_signext; // sfix20_En20
  wire signed [19:0] add_signext_1; // sfix20_En20
  wire signed [20:0] add_temp; // sfix21_En20
  wire signed [19:0] sum2; // sfix20_En20
  wire signed [19:0] add_signext_2; // sfix20_En20
  wire signed [19:0] add_signext_3; // sfix20_En20
  wire signed [20:0] add_temp_1; // sfix21_En20
  wire signed [19:0] sum3; // sfix20_En20
  wire signed [19:0] add_signext_4; // sfix20_En20
  wire signed [19:0] add_signext_5; // sfix20_En20
  wire signed [20:0] add_temp_2; // sfix21_En20
  wire signed [19:0] sum4; // sfix20_En20
  wire signed [19:0] add_signext_6; // sfix20_En20
  wire signed [19:0] add_signext_7; // sfix20_En20
  wire signed [20:0] add_temp_3; // sfix21_En20
  wire signed [19:0] sum5; // sfix20_En20
  wire signed [19:0] add_signext_8; // sfix20_En20
  wire signed [19:0] add_signext_9; // sfix20_En20
  wire signed [20:0] add_temp_4; // sfix21_En20
  wire signed [19:0] sum6; // sfix20_En20
  wire signed [19:0] add_signext_10; // sfix20_En20
  wire signed [19:0] add_signext_11; // sfix20_En20
  wire signed [20:0] add_temp_5; // sfix21_En20
  wire signed [19:0] sum7; // sfix20_En20
  wire signed [19:0] add_signext_12; // sfix20_En20
  wire signed [19:0] add_signext_13; // sfix20_En20
  wire signed [20:0] add_temp_6; // sfix21_En20
  wire signed [19:0] sum8; // sfix20_En20
  wire signed [19:0] add_signext_14; // sfix20_En20
  wire signed [19:0] add_signext_15; // sfix20_En20
  wire signed [20:0] add_temp_7; // sfix21_En20
  wire signed [19:0] sum9; // sfix20_En20
  wire signed [19:0] add_signext_16; // sfix20_En20
  wire signed [19:0] add_signext_17; // sfix20_En20
  wire signed [20:0] add_temp_8; // sfix21_En20
  wire signed [19:0] sum10; // sfix20_En20
  wire signed [19:0] add_signext_18; // sfix20_En20
  wire signed [19:0] add_signext_19; // sfix20_En20
  wire signed [20:0] add_temp_9; // sfix21_En20
  wire signed [19:0] sum11; // sfix20_En20
  wire signed [19:0] add_signext_20; // sfix20_En20
  wire signed [19:0] add_signext_21; // sfix20_En20
  wire signed [20:0] add_temp_10; // sfix21_En20
  wire signed [19:0] sum12; // sfix20_En20
  wire signed [19:0] add_signext_22; // sfix20_En20
  wire signed [19:0] add_signext_23; // sfix20_En20
  wire signed [20:0] add_temp_11; // sfix21_En20
  wire signed [19:0] sum13; // sfix20_En20
  wire signed [19:0] add_signext_24; // sfix20_En20
  wire signed [19:0] add_signext_25; // sfix20_En20
  wire signed [20:0] add_temp_12; // sfix21_En20
  wire signed [19:0] sum14; // sfix20_En20
  wire signed [19:0] add_signext_26; // sfix20_En20
  wire signed [19:0] add_signext_27; // sfix20_En20
  wire signed [20:0] add_temp_13; // sfix21_En20
  wire signed [19:0] sum15; // sfix20_En20
  wire signed [19:0] add_signext_28; // sfix20_En20
  wire signed [19:0] add_signext_29; // sfix20_En20
  wire signed [20:0] add_temp_14; // sfix21_En20
  wire signed [19:0] sum16; // sfix20_En20
  wire signed [19:0] add_signext_30; // sfix20_En20
  wire signed [19:0] add_signext_31; // sfix20_En20
  wire signed [20:0] add_temp_15; // sfix21_En20
  wire signed [19:0] sum17; // sfix20_En20
  wire signed [19:0] add_signext_32; // sfix20_En20
  wire signed [19:0] add_signext_33; // sfix20_En20
  wire signed [20:0] add_temp_16; // sfix21_En20
  wire signed [19:0] sum18; // sfix20_En20
  wire signed [19:0] add_signext_34; // sfix20_En20
  wire signed [19:0] add_signext_35; // sfix20_En20
  wire signed [20:0] add_temp_17; // sfix21_En20
  wire signed [19:0] sum19; // sfix20_En20
  wire signed [19:0] add_signext_36; // sfix20_En20
  wire signed [19:0] add_signext_37; // sfix20_En20
  wire signed [20:0] add_temp_18; // sfix21_En20
  wire signed [19:0] sum20; // sfix20_En20
  wire signed [19:0] add_signext_38; // sfix20_En20
  wire signed [19:0] add_signext_39; // sfix20_En20
  wire signed [20:0] add_temp_19; // sfix21_En20
  wire signed [19:0] sum21; // sfix20_En20
  wire signed [19:0] add_signext_40; // sfix20_En20
  wire signed [19:0] add_signext_41; // sfix20_En20
  wire signed [20:0] add_temp_20; // sfix21_En20
  wire signed [19:0] sum22; // sfix20_En20
  wire signed [19:0] add_signext_42; // sfix20_En20
  wire signed [19:0] add_signext_43; // sfix20_En20
  wire signed [20:0] add_temp_21; // sfix21_En20
  wire signed [19:0] sum23; // sfix20_En20
  wire signed [19:0] add_signext_44; // sfix20_En20
  wire signed [19:0] add_signext_45; // sfix20_En20
  wire signed [20:0] add_temp_22; // sfix21_En20
  wire signed [19:0] sum24; // sfix20_En20
  wire signed [19:0] add_signext_46; // sfix20_En20
  wire signed [19:0] add_signext_47; // sfix20_En20
  wire signed [20:0] add_temp_23; // sfix21_En20
  wire signed [19:0] sum25; // sfix20_En20
  wire signed [19:0] add_signext_48; // sfix20_En20
  wire signed [19:0] add_signext_49; // sfix20_En20
  wire signed [20:0] add_temp_24; // sfix21_En20
  wire signed [19:0] sum26; // sfix20_En20
  wire signed [19:0] add_signext_50; // sfix20_En20
  wire signed [19:0] add_signext_51; // sfix20_En20
  wire signed [20:0] add_temp_25; // sfix21_En20
  wire signed [19:0] sum27; // sfix20_En20
  wire signed [19:0] add_signext_52; // sfix20_En20
  wire signed [19:0] add_signext_53; // sfix20_En20
  wire signed [20:0] add_temp_26; // sfix21_En20
  wire signed [19:0] sum28; // sfix20_En20
  wire signed [19:0] add_signext_54; // sfix20_En20
  wire signed [19:0] add_signext_55; // sfix20_En20
  wire signed [20:0] add_temp_27; // sfix21_En20
  wire signed [19:0] sum29; // sfix20_En20
  wire signed [19:0] add_signext_56; // sfix20_En20
  wire signed [19:0] add_signext_57; // sfix20_En20
  wire signed [20:0] add_temp_28; // sfix21_En20
  wire signed [19:0] sum30; // sfix20_En20
  wire signed [19:0] add_signext_58; // sfix20_En20
  wire signed [19:0] add_signext_59; // sfix20_En20
  wire signed [20:0] add_temp_29; // sfix21_En20
  wire signed [19:0] sum31; // sfix20_En20
  wire signed [19:0] add_signext_60; // sfix20_En20
  wire signed [19:0] add_signext_61; // sfix20_En20
  wire signed [20:0] add_temp_30; // sfix21_En20
  wire signed [19:0] sum32; // sfix20_En20
  wire signed [19:0] add_signext_62; // sfix20_En20
  wire signed [19:0] add_signext_63; // sfix20_En20
  wire signed [20:0] add_temp_31; // sfix21_En20
  wire signed [19:0] sum33; // sfix20_En20
  wire signed [19:0] add_signext_64; // sfix20_En20
  wire signed [19:0] add_signext_65; // sfix20_En20
  wire signed [20:0] add_temp_32; // sfix21_En20
  wire signed [19:0] sum34; // sfix20_En20
  wire signed [19:0] add_signext_66; // sfix20_En20
  wire signed [19:0] add_signext_67; // sfix20_En20
  wire signed [20:0] add_temp_33; // sfix21_En20
  wire signed [19:0] sum35; // sfix20_En20
  wire signed [19:0] add_signext_68; // sfix20_En20
  wire signed [19:0] add_signext_69; // sfix20_En20
  wire signed [20:0] add_temp_34; // sfix21_En20
  wire signed [19:0] sum36; // sfix20_En20
  wire signed [19:0] add_signext_70; // sfix20_En20
  wire signed [19:0] add_signext_71; // sfix20_En20
  wire signed [20:0] add_temp_35; // sfix21_En20
  wire signed [19:0] sum37; // sfix20_En20
  wire signed [19:0] add_signext_72; // sfix20_En20
  wire signed [19:0] add_signext_73; // sfix20_En20
  wire signed [20:0] add_temp_36; // sfix21_En20
  wire signed [19:0] sum38; // sfix20_En20
  wire signed [19:0] add_signext_74; // sfix20_En20
  wire signed [19:0] add_signext_75; // sfix20_En20
  wire signed [20:0] add_temp_37; // sfix21_En20
  wire signed [19:0] sum39; // sfix20_En20
  wire signed [19:0] add_signext_76; // sfix20_En20
  wire signed [19:0] add_signext_77; // sfix20_En20
  wire signed [20:0] add_temp_38; // sfix21_En20
  wire signed [19:0] sum40; // sfix20_En20
  wire signed [19:0] add_signext_78; // sfix20_En20
  wire signed [19:0] add_signext_79; // sfix20_En20
  wire signed [20:0] add_temp_39; // sfix21_En20
  wire signed [19:0] sum41; // sfix20_En20
  wire signed [19:0] add_signext_80; // sfix20_En20
  wire signed [19:0] add_signext_81; // sfix20_En20
  wire signed [20:0] add_temp_40; // sfix21_En20
  wire signed [19:0] sum42; // sfix20_En20
  wire signed [19:0] add_signext_82; // sfix20_En20
  wire signed [19:0] add_signext_83; // sfix20_En20
  wire signed [20:0] add_temp_41; // sfix21_En20
  wire signed [19:0] sum43; // sfix20_En20
  wire signed [19:0] add_signext_84; // sfix20_En20
  wire signed [19:0] add_signext_85; // sfix20_En20
  wire signed [20:0] add_temp_42; // sfix21_En20
  wire signed [19:0] sum44; // sfix20_En20
  wire signed [19:0] add_signext_86; // sfix20_En20
  wire signed [19:0] add_signext_87; // sfix20_En20
  wire signed [20:0] add_temp_43; // sfix21_En20
  wire signed [19:0] sum45; // sfix20_En20
  wire signed [19:0] add_signext_88; // sfix20_En20
  wire signed [19:0] add_signext_89; // sfix20_En20
  wire signed [20:0] add_temp_44; // sfix21_En20
  wire signed [19:0] sum46; // sfix20_En20
  wire signed [19:0] add_signext_90; // sfix20_En20
  wire signed [19:0] add_signext_91; // sfix20_En20
  wire signed [20:0] add_temp_45; // sfix21_En20
  wire signed [19:0] sum47; // sfix20_En20
  wire signed [19:0] add_signext_92; // sfix20_En20
  wire signed [19:0] add_signext_93; // sfix20_En20
  wire signed [20:0] add_temp_46; // sfix21_En20
  wire signed [19:0] sum48; // sfix20_En20
  wire signed [19:0] add_signext_94; // sfix20_En20
  wire signed [19:0] add_signext_95; // sfix20_En20
  wire signed [20:0] add_temp_47; // sfix21_En20
  wire signed [19:0] sum49; // sfix20_En20
  wire signed [19:0] add_signext_96; // sfix20_En20
  wire signed [19:0] add_signext_97; // sfix20_En20
  wire signed [20:0] add_temp_48; // sfix21_En20
  wire signed [19:0] sum50; // sfix20_En20
  wire signed [19:0] add_signext_98; // sfix20_En20
  wire signed [19:0] add_signext_99; // sfix20_En20
  wire signed [20:0] add_temp_49; // sfix21_En20
  wire signed [7:0] output_typeconvert; // sfix8_En32
  reg  signed [7:0] output_register; // sfix8_En32

  // Block Statements
  always @( posedge clk or posedge reset)
    begin: Delay_Pipeline_process
      if (reset == 1'b1) begin
        delay_pipeline[0] <= 0;
        delay_pipeline[1] <= 0;
        delay_pipeline[2] <= 0;
        delay_pipeline[3] <= 0;
        delay_pipeline[4] <= 0;
        delay_pipeline[5] <= 0;
        delay_pipeline[6] <= 0;
        delay_pipeline[7] <= 0;
        delay_pipeline[8] <= 0;
        delay_pipeline[9] <= 0;
        delay_pipeline[10] <= 0;
        delay_pipeline[11] <= 0;
        delay_pipeline[12] <= 0;
        delay_pipeline[13] <= 0;
        delay_pipeline[14] <= 0;
        delay_pipeline[15] <= 0;
        delay_pipeline[16] <= 0;
        delay_pipeline[17] <= 0;
        delay_pipeline[18] <= 0;
        delay_pipeline[19] <= 0;
        delay_pipeline[20] <= 0;
        delay_pipeline[21] <= 0;
        delay_pipeline[22] <= 0;
        delay_pipeline[23] <= 0;
        delay_pipeline[24] <= 0;
        delay_pipeline[25] <= 0;
        delay_pipeline[26] <= 0;
        delay_pipeline[27] <= 0;
        delay_pipeline[28] <= 0;
        delay_pipeline[29] <= 0;
        delay_pipeline[30] <= 0;
        delay_pipeline[31] <= 0;
        delay_pipeline[32] <= 0;
        delay_pipeline[33] <= 0;
        delay_pipeline[34] <= 0;
        delay_pipeline[35] <= 0;
        delay_pipeline[36] <= 0;
        delay_pipeline[37] <= 0;
        delay_pipeline[38] <= 0;
        delay_pipeline[39] <= 0;
        delay_pipeline[40] <= 0;
        delay_pipeline[41] <= 0;
        delay_pipeline[42] <= 0;
        delay_pipeline[43] <= 0;
        delay_pipeline[44] <= 0;
        delay_pipeline[45] <= 0;
        delay_pipeline[46] <= 0;
        delay_pipeline[47] <= 0;
        delay_pipeline[48] <= 0;
        delay_pipeline[49] <= 0;
      end
      else begin
        if (clk_enable == 1'b1) begin
          delay_pipeline[0] <= data_in;
          delay_pipeline[1] <= delay_pipeline[0];
          delay_pipeline[2] <= delay_pipeline[1];
          delay_pipeline[3] <= delay_pipeline[2];
          delay_pipeline[4] <= delay_pipeline[3];
          delay_pipeline[5] <= delay_pipeline[4];
          delay_pipeline[6] <= delay_pipeline[5];
          delay_pipeline[7] <= delay_pipeline[6];
          delay_pipeline[8] <= delay_pipeline[7];
          delay_pipeline[9] <= delay_pipeline[8];
          delay_pipeline[10] <= delay_pipeline[9];
          delay_pipeline[11] <= delay_pipeline[10];
          delay_pipeline[12] <= delay_pipeline[11];
          delay_pipeline[13] <= delay_pipeline[12];
          delay_pipeline[14] <= delay_pipeline[13];
          delay_pipeline[15] <= delay_pipeline[14];
          delay_pipeline[16] <= delay_pipeline[15];
          delay_pipeline[17] <= delay_pipeline[16];
          delay_pipeline[18] <= delay_pipeline[17];
          delay_pipeline[19] <= delay_pipeline[18];
          delay_pipeline[20] <= delay_pipeline[19];
          delay_pipeline[21] <= delay_pipeline[20];
          delay_pipeline[22] <= delay_pipeline[21];
          delay_pipeline[23] <= delay_pipeline[22];
          delay_pipeline[24] <= delay_pipeline[23];
          delay_pipeline[25] <= delay_pipeline[24];
          delay_pipeline[26] <= delay_pipeline[25];
          delay_pipeline[27] <= delay_pipeline[26];
          delay_pipeline[28] <= delay_pipeline[27];
          delay_pipeline[29] <= delay_pipeline[28];
          delay_pipeline[30] <= delay_pipeline[29];
          delay_pipeline[31] <= delay_pipeline[30];
          delay_pipeline[32] <= delay_pipeline[31];
          delay_pipeline[33] <= delay_pipeline[32];
          delay_pipeline[34] <= delay_pipeline[33];
          delay_pipeline[35] <= delay_pipeline[34];
          delay_pipeline[36] <= delay_pipeline[35];
          delay_pipeline[37] <= delay_pipeline[36];
          delay_pipeline[38] <= delay_pipeline[37];
          delay_pipeline[39] <= delay_pipeline[38];
          delay_pipeline[40] <= delay_pipeline[39];
          delay_pipeline[41] <= delay_pipeline[40];
          delay_pipeline[42] <= delay_pipeline[41];
          delay_pipeline[43] <= delay_pipeline[42];
          delay_pipeline[44] <= delay_pipeline[43];
          delay_pipeline[45] <= delay_pipeline[44];
          delay_pipeline[46] <= delay_pipeline[45];
          delay_pipeline[47] <= delay_pipeline[46];
          delay_pipeline[48] <= delay_pipeline[47];
          delay_pipeline[49] <= delay_pipeline[48];
        end
      end
    end // Delay_Pipeline_process


  assign mul_temp = delay_pipeline[49] * coeff51;
  assign product51 = $signed({{1{mul_temp[21]}}, mul_temp[21:7]});

  assign mul_temp_1 = delay_pipeline[48] * coeff50;
  assign product50 = $signed({{1{mul_temp_1[21]}}, mul_temp_1[21:7]});

  assign mul_temp_2 = delay_pipeline[47] * coeff49;
  assign product49 = $signed({{1{mul_temp_2[21]}}, mul_temp_2[21:7]});

  assign mul_temp_3 = delay_pipeline[46] * coeff48;
  assign product48 = $signed({{1{mul_temp_3[21]}}, mul_temp_3[21:7]});

  assign mul_temp_4 = delay_pipeline[45] * coeff47;
  assign product47 = $signed({{1{mul_temp_4[21]}}, mul_temp_4[21:7]});

  assign mul_temp_5 = delay_pipeline[44] * coeff46;
  assign product46 = $signed({{1{mul_temp_5[21]}}, mul_temp_5[21:7]});

  assign mul_temp_6 = delay_pipeline[43] * coeff45;
  assign product45 = $signed({{1{mul_temp_6[21]}}, mul_temp_6[21:7]});

  assign mul_temp_7 = delay_pipeline[42] * coeff44;
  assign product44 = $signed({{1{mul_temp_7[21]}}, mul_temp_7[21:7]});

  assign mul_temp_8 = delay_pipeline[41] * coeff43;
  assign product43 = $signed({{1{mul_temp_8[21]}}, mul_temp_8[21:7]});

  assign mul_temp_9 = delay_pipeline[40] * coeff42;
  assign product42 = $signed({{1{mul_temp_9[21]}}, mul_temp_9[21:7]});

  assign mul_temp_10 = delay_pipeline[39] * coeff41;
  assign product41 = $signed({{1{mul_temp_10[21]}}, mul_temp_10[21:7]});

  assign mul_temp_11 = delay_pipeline[38] * coeff40;
  assign product40 = $signed({{1{mul_temp_11[21]}}, mul_temp_11[21:7]});

  assign mul_temp_12 = delay_pipeline[37] * coeff39;
  assign product39 = $signed({{1{mul_temp_12[21]}}, mul_temp_12[21:7]});

  assign mul_temp_13 = delay_pipeline[36] * coeff38;
  assign product38 = $signed({{1{mul_temp_13[21]}}, mul_temp_13[21:7]});

  assign mul_temp_14 = delay_pipeline[35] * coeff37;
  assign product37 = $signed({{1{mul_temp_14[21]}}, mul_temp_14[21:7]});

  assign mulpwr2_temp = (delay_pipeline[34]==8'b10000000) ? $signed({1'b0, delay_pipeline[34]}) : -delay_pipeline[34];

  assign product36 = $signed({{14{mulpwr2_temp[8]}}, mulpwr2_temp[8:7]});

  assign mul_temp_15 = delay_pipeline[33] * coeff35;
  assign product35 = $signed({{1{mul_temp_15[21]}}, mul_temp_15[21:7]});

  assign mul_temp_16 = delay_pipeline[32] * coeff34;
  assign product34 = $signed({{1{mul_temp_16[21]}}, mul_temp_16[21:7]});

  assign mul_temp_17 = delay_pipeline[31] * coeff33;
  assign product33 = $signed({{1{mul_temp_17[21]}}, mul_temp_17[21:7]});

  assign mul_temp_18 = delay_pipeline[30] * coeff32;
  assign product32 = $signed({{1{mul_temp_18[21]}}, mul_temp_18[21:7]});

  assign mul_temp_19 = delay_pipeline[29] * coeff31;
  assign product31 = $signed({{1{mul_temp_19[21]}}, mul_temp_19[21:7]});

  assign mul_temp_20 = delay_pipeline[28] * coeff30;
  assign product30 = $signed({{1{mul_temp_20[21]}}, mul_temp_20[21:7]});

  assign mul_temp_21 = delay_pipeline[27] * coeff29;
  assign product29 = $signed({{1{mul_temp_21[21]}}, mul_temp_21[21:7]});

  assign mul_temp_22 = delay_pipeline[26] * coeff28;
  assign product28 = $signed({{1{mul_temp_22[21]}}, mul_temp_22[21:7]});

  assign mul_temp_23 = delay_pipeline[25] * coeff27;
  assign product27 = $signed({{1{mul_temp_23[21]}}, mul_temp_23[21:7]});

  assign mul_temp_24 = delay_pipeline[24] * coeff26;
  assign product26 = $signed({{1{mul_temp_24[21]}}, mul_temp_24[21:7]});

  assign mul_temp_25 = delay_pipeline[23] * coeff25;
  assign product25 = $signed({{1{mul_temp_25[21]}}, mul_temp_25[21:7]});

  assign mul_temp_26 = delay_pipeline[22] * coeff24;
  assign product24 = $signed({{1{mul_temp_26[21]}}, mul_temp_26[21:7]});

  assign mul_temp_27 = delay_pipeline[21] * coeff23;
  assign product23 = $signed({{1{mul_temp_27[21]}}, mul_temp_27[21:7]});

  assign mul_temp_28 = delay_pipeline[20] * coeff22;
  assign product22 = $signed({{1{mul_temp_28[21]}}, mul_temp_28[21:7]});

  assign mul_temp_29 = delay_pipeline[19] * coeff21;
  assign product21 = $signed({{1{mul_temp_29[21]}}, mul_temp_29[21:7]});

  assign mul_temp_30 = delay_pipeline[18] * coeff20;
  assign product20 = $signed({{1{mul_temp_30[21]}}, mul_temp_30[21:7]});

  assign mul_temp_31 = delay_pipeline[17] * coeff19;
  assign product19 = $signed({{1{mul_temp_31[21]}}, mul_temp_31[21:7]});

  assign mul_temp_32 = delay_pipeline[16] * coeff18;
  assign product18 = $signed({{1{mul_temp_32[21]}}, mul_temp_32[21:7]});

  assign mul_temp_33 = delay_pipeline[15] * coeff17;
  assign product17 = $signed({{1{mul_temp_33[21]}}, mul_temp_33[21:7]});

  assign mulpwr2_temp_1 = (delay_pipeline[14]==8'b10000000) ? $signed({1'b0, delay_pipeline[14]}) : -delay_pipeline[14];

  assign product16 = $signed({{14{mulpwr2_temp_1[8]}}, mulpwr2_temp_1[8:7]});

  assign mul_temp_34 = delay_pipeline[13] * coeff15;
  assign product15 = $signed({{1{mul_temp_34[21]}}, mul_temp_34[21:7]});

  assign mul_temp_35 = delay_pipeline[12] * coeff14;
  assign product14 = $signed({{1{mul_temp_35[21]}}, mul_temp_35[21:7]});

  assign mul_temp_36 = delay_pipeline[11] * coeff13;
  assign product13 = $signed({{1{mul_temp_36[21]}}, mul_temp_36[21:7]});

  assign mul_temp_37 = delay_pipeline[10] * coeff12;
  assign product12 = $signed({{1{mul_temp_37[21]}}, mul_temp_37[21:7]});

  assign mul_temp_38 = delay_pipeline[9] * coeff11;
  assign product11 = $signed({{1{mul_temp_38[21]}}, mul_temp_38[21:7]});

  assign mul_temp_39 = delay_pipeline[8] * coeff10;
  assign product10 = $signed({{1{mul_temp_39[21]}}, mul_temp_39[21:7]});

  assign mul_temp_40 = delay_pipeline[7] * coeff9;
  assign product9 = $signed({{1{mul_temp_40[21]}}, mul_temp_40[21:7]});

  assign mul_temp_41 = delay_pipeline[6] * coeff8;
  assign product8 = $signed({{1{mul_temp_41[21]}}, mul_temp_41[21:7]});

  assign mul_temp_42 = delay_pipeline[5] * coeff7;
  assign product7 = $signed({{1{mul_temp_42[21]}}, mul_temp_42[21:7]});

  assign mul_temp_43 = delay_pipeline[4] * coeff6;
  assign product6 = $signed({{1{mul_temp_43[21]}}, mul_temp_43[21:7]});

  assign mul_temp_44 = delay_pipeline[3] * coeff5;
  assign product5 = $signed({{1{mul_temp_44[21]}}, mul_temp_44[21:7]});

  assign mul_temp_45 = delay_pipeline[2] * coeff4;
  assign product4 = $signed({{1{mul_temp_45[21]}}, mul_temp_45[21:7]});

  assign mul_temp_46 = delay_pipeline[1] * coeff3;
  assign product3 = $signed({{1{mul_temp_46[21]}}, mul_temp_46[21:7]});

  assign mul_temp_47 = delay_pipeline[0] * coeff2;
  assign product2 = $signed({{1{mul_temp_47[21]}}, mul_temp_47[21:7]});

  assign product1_cast = $signed({product1, 3'b000});

  assign mul_temp_48 = data_in * coeff1;
  assign product1 = $signed({{1{mul_temp_48[21]}}, mul_temp_48[21:7]});

  assign add_signext = product1_cast;
  assign add_signext_1 = $signed({product2[15:0], 3'b000});
  assign add_temp = add_signext + add_signext_1;
  assign sum1 = (add_temp[20] == 1'b0 & add_temp[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp[20] == 1'b1 && add_temp[19] != 1'b1) ? 20'b10000000000000000000 : add_temp[19:0];

  assign add_signext_2 = sum1;
  assign add_signext_3 = $signed({product3[15:0], 3'b000});
  assign add_temp_1 = add_signext_2 + add_signext_3;
  assign sum2 = (add_temp_1[20] == 1'b0 & add_temp_1[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_1[20] == 1'b1 && add_temp_1[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_1[19:0];

  assign add_signext_4 = sum2;
  assign add_signext_5 = $signed({product4[15:0], 3'b000});
  assign add_temp_2 = add_signext_4 + add_signext_5;
  assign sum3 = (add_temp_2[20] == 1'b0 & add_temp_2[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_2[20] == 1'b1 && add_temp_2[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_2[19:0];

  assign add_signext_6 = sum3;
  assign add_signext_7 = $signed({product5[15:0], 3'b000});
  assign add_temp_3 = add_signext_6 + add_signext_7;
  assign sum4 = (add_temp_3[20] == 1'b0 & add_temp_3[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_3[20] == 1'b1 && add_temp_3[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_3[19:0];

  assign add_signext_8 = sum4;
  assign add_signext_9 = $signed({product6[15:0], 3'b000});
  assign add_temp_4 = add_signext_8 + add_signext_9;
  assign sum5 = (add_temp_4[20] == 1'b0 & add_temp_4[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_4[20] == 1'b1 && add_temp_4[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_4[19:0];

  assign add_signext_10 = sum5;
  assign add_signext_11 = $signed({product7[15:0], 3'b000});
  assign add_temp_5 = add_signext_10 + add_signext_11;
  assign sum6 = (add_temp_5[20] == 1'b0 & add_temp_5[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_5[20] == 1'b1 && add_temp_5[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_5[19:0];

  assign add_signext_12 = sum6;
  assign add_signext_13 = $signed({product8[15:0], 3'b000});
  assign add_temp_6 = add_signext_12 + add_signext_13;
  assign sum7 = (add_temp_6[20] == 1'b0 & add_temp_6[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_6[20] == 1'b1 && add_temp_6[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_6[19:0];

  assign add_signext_14 = sum7;
  assign add_signext_15 = $signed({product9[15:0], 3'b000});
  assign add_temp_7 = add_signext_14 + add_signext_15;
  assign sum8 = (add_temp_7[20] == 1'b0 & add_temp_7[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_7[20] == 1'b1 && add_temp_7[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_7[19:0];

  assign add_signext_16 = sum8;
  assign add_signext_17 = $signed({product10[15:0], 3'b000});
  assign add_temp_8 = add_signext_16 + add_signext_17;
  assign sum9 = (add_temp_8[20] == 1'b0 & add_temp_8[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_8[20] == 1'b1 && add_temp_8[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_8[19:0];

  assign add_signext_18 = sum9;
  assign add_signext_19 = $signed({product11[15:0], 3'b000});
  assign add_temp_9 = add_signext_18 + add_signext_19;
  assign sum10 = (add_temp_9[20] == 1'b0 & add_temp_9[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_9[20] == 1'b1 && add_temp_9[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_9[19:0];

  assign add_signext_20 = sum10;
  assign add_signext_21 = $signed({product12[15:0], 3'b000});
  assign add_temp_10 = add_signext_20 + add_signext_21;
  assign sum11 = (add_temp_10[20] == 1'b0 & add_temp_10[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_10[20] == 1'b1 && add_temp_10[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_10[19:0];

  assign add_signext_22 = sum11;
  assign add_signext_23 = $signed({product13[15:0], 3'b000});
  assign add_temp_11 = add_signext_22 + add_signext_23;
  assign sum12 = (add_temp_11[20] == 1'b0 & add_temp_11[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_11[20] == 1'b1 && add_temp_11[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_11[19:0];

  assign add_signext_24 = sum12;
  assign add_signext_25 = $signed({product14[15:0], 3'b000});
  assign add_temp_12 = add_signext_24 + add_signext_25;
  assign sum13 = (add_temp_12[20] == 1'b0 & add_temp_12[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_12[20] == 1'b1 && add_temp_12[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_12[19:0];

  assign add_signext_26 = sum13;
  assign add_signext_27 = $signed({product15[15:0], 3'b000});
  assign add_temp_13 = add_signext_26 + add_signext_27;
  assign sum14 = (add_temp_13[20] == 1'b0 & add_temp_13[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_13[20] == 1'b1 && add_temp_13[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_13[19:0];

  assign add_signext_28 = sum14;
  assign add_signext_29 = $signed({product16[15:0], 3'b000});
  assign add_temp_14 = add_signext_28 + add_signext_29;
  assign sum15 = (add_temp_14[20] == 1'b0 & add_temp_14[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_14[20] == 1'b1 && add_temp_14[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_14[19:0];

  assign add_signext_30 = sum15;
  assign add_signext_31 = $signed({product17[15:0], 3'b000});
  assign add_temp_15 = add_signext_30 + add_signext_31;
  assign sum16 = (add_temp_15[20] == 1'b0 & add_temp_15[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_15[20] == 1'b1 && add_temp_15[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_15[19:0];

  assign add_signext_32 = sum16;
  assign add_signext_33 = $signed({product18[15:0], 3'b000});
  assign add_temp_16 = add_signext_32 + add_signext_33;
  assign sum17 = (add_temp_16[20] == 1'b0 & add_temp_16[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_16[20] == 1'b1 && add_temp_16[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_16[19:0];

  assign add_signext_34 = sum17;
  assign add_signext_35 = $signed({product19[15:0], 3'b000});
  assign add_temp_17 = add_signext_34 + add_signext_35;
  assign sum18 = (add_temp_17[20] == 1'b0 & add_temp_17[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_17[20] == 1'b1 && add_temp_17[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_17[19:0];

  assign add_signext_36 = sum18;
  assign add_signext_37 = $signed({product20[15:0], 3'b000});
  assign add_temp_18 = add_signext_36 + add_signext_37;
  assign sum19 = (add_temp_18[20] == 1'b0 & add_temp_18[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_18[20] == 1'b1 && add_temp_18[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_18[19:0];

  assign add_signext_38 = sum19;
  assign add_signext_39 = $signed({product21[15:0], 3'b000});
  assign add_temp_19 = add_signext_38 + add_signext_39;
  assign sum20 = (add_temp_19[20] == 1'b0 & add_temp_19[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_19[20] == 1'b1 && add_temp_19[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_19[19:0];

  assign add_signext_40 = sum20;
  assign add_signext_41 = $signed({product22[15:0], 3'b000});
  assign add_temp_20 = add_signext_40 + add_signext_41;
  assign sum21 = (add_temp_20[20] == 1'b0 & add_temp_20[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_20[20] == 1'b1 && add_temp_20[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_20[19:0];

  assign add_signext_42 = sum21;
  assign add_signext_43 = $signed({product23[15:0], 3'b000});
  assign add_temp_21 = add_signext_42 + add_signext_43;
  assign sum22 = (add_temp_21[20] == 1'b0 & add_temp_21[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_21[20] == 1'b1 && add_temp_21[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_21[19:0];

  assign add_signext_44 = sum22;
  assign add_signext_45 = $signed({product24[15:0], 3'b000});
  assign add_temp_22 = add_signext_44 + add_signext_45;
  assign sum23 = (add_temp_22[20] == 1'b0 & add_temp_22[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_22[20] == 1'b1 && add_temp_22[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_22[19:0];

  assign add_signext_46 = sum23;
  assign add_signext_47 = $signed({product25[15:0], 3'b000});
  assign add_temp_23 = add_signext_46 + add_signext_47;
  assign sum24 = (add_temp_23[20] == 1'b0 & add_temp_23[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_23[20] == 1'b1 && add_temp_23[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_23[19:0];

  assign add_signext_48 = sum24;
  assign add_signext_49 = $signed({product26[15:0], 3'b000});
  assign add_temp_24 = add_signext_48 + add_signext_49;
  assign sum25 = (add_temp_24[20] == 1'b0 & add_temp_24[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_24[20] == 1'b1 && add_temp_24[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_24[19:0];

  assign add_signext_50 = sum25;
  assign add_signext_51 = $signed({product27[15:0], 3'b000});
  assign add_temp_25 = add_signext_50 + add_signext_51;
  assign sum26 = (add_temp_25[20] == 1'b0 & add_temp_25[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_25[20] == 1'b1 && add_temp_25[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_25[19:0];

  assign add_signext_52 = sum26;
  assign add_signext_53 = $signed({product28[15:0], 3'b000});
  assign add_temp_26 = add_signext_52 + add_signext_53;
  assign sum27 = (add_temp_26[20] == 1'b0 & add_temp_26[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_26[20] == 1'b1 && add_temp_26[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_26[19:0];

  assign add_signext_54 = sum27;
  assign add_signext_55 = $signed({product29[15:0], 3'b000});
  assign add_temp_27 = add_signext_54 + add_signext_55;
  assign sum28 = (add_temp_27[20] == 1'b0 & add_temp_27[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_27[20] == 1'b1 && add_temp_27[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_27[19:0];

  assign add_signext_56 = sum28;
  assign add_signext_57 = $signed({product30[15:0], 3'b000});
  assign add_temp_28 = add_signext_56 + add_signext_57;
  assign sum29 = (add_temp_28[20] == 1'b0 & add_temp_28[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_28[20] == 1'b1 && add_temp_28[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_28[19:0];

  assign add_signext_58 = sum29;
  assign add_signext_59 = $signed({product31[15:0], 3'b000});
  assign add_temp_29 = add_signext_58 + add_signext_59;
  assign sum30 = (add_temp_29[20] == 1'b0 & add_temp_29[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_29[20] == 1'b1 && add_temp_29[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_29[19:0];

  assign add_signext_60 = sum30;
  assign add_signext_61 = $signed({product32[15:0], 3'b000});
  assign add_temp_30 = add_signext_60 + add_signext_61;
  assign sum31 = (add_temp_30[20] == 1'b0 & add_temp_30[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_30[20] == 1'b1 && add_temp_30[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_30[19:0];

  assign add_signext_62 = sum31;
  assign add_signext_63 = $signed({product33[15:0], 3'b000});
  assign add_temp_31 = add_signext_62 + add_signext_63;
  assign sum32 = (add_temp_31[20] == 1'b0 & add_temp_31[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_31[20] == 1'b1 && add_temp_31[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_31[19:0];

  assign add_signext_64 = sum32;
  assign add_signext_65 = $signed({product34[15:0], 3'b000});
  assign add_temp_32 = add_signext_64 + add_signext_65;
  assign sum33 = (add_temp_32[20] == 1'b0 & add_temp_32[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_32[20] == 1'b1 && add_temp_32[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_32[19:0];

  assign add_signext_66 = sum33;
  assign add_signext_67 = $signed({product35[15:0], 3'b000});
  assign add_temp_33 = add_signext_66 + add_signext_67;
  assign sum34 = (add_temp_33[20] == 1'b0 & add_temp_33[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_33[20] == 1'b1 && add_temp_33[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_33[19:0];

  assign add_signext_68 = sum34;
  assign add_signext_69 = $signed({product36[15:0], 3'b000});
  assign add_temp_34 = add_signext_68 + add_signext_69;
  assign sum35 = (add_temp_34[20] == 1'b0 & add_temp_34[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_34[20] == 1'b1 && add_temp_34[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_34[19:0];

  assign add_signext_70 = sum35;
  assign add_signext_71 = $signed({product37[15:0], 3'b000});
  assign add_temp_35 = add_signext_70 + add_signext_71;
  assign sum36 = (add_temp_35[20] == 1'b0 & add_temp_35[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_35[20] == 1'b1 && add_temp_35[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_35[19:0];

  assign add_signext_72 = sum36;
  assign add_signext_73 = $signed({product38[15:0], 3'b000});
  assign add_temp_36 = add_signext_72 + add_signext_73;
  assign sum37 = (add_temp_36[20] == 1'b0 & add_temp_36[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_36[20] == 1'b1 && add_temp_36[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_36[19:0];

  assign add_signext_74 = sum37;
  assign add_signext_75 = $signed({product39[15:0], 3'b000});
  assign add_temp_37 = add_signext_74 + add_signext_75;
  assign sum38 = (add_temp_37[20] == 1'b0 & add_temp_37[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_37[20] == 1'b1 && add_temp_37[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_37[19:0];

  assign add_signext_76 = sum38;
  assign add_signext_77 = $signed({product40[15:0], 3'b000});
  assign add_temp_38 = add_signext_76 + add_signext_77;
  assign sum39 = (add_temp_38[20] == 1'b0 & add_temp_38[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_38[20] == 1'b1 && add_temp_38[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_38[19:0];

  assign add_signext_78 = sum39;
  assign add_signext_79 = $signed({product41[15:0], 3'b000});
  assign add_temp_39 = add_signext_78 + add_signext_79;
  assign sum40 = (add_temp_39[20] == 1'b0 & add_temp_39[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_39[20] == 1'b1 && add_temp_39[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_39[19:0];

  assign add_signext_80 = sum40;
  assign add_signext_81 = $signed({product42[15:0], 3'b000});
  assign add_temp_40 = add_signext_80 + add_signext_81;
  assign sum41 = (add_temp_40[20] == 1'b0 & add_temp_40[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_40[20] == 1'b1 && add_temp_40[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_40[19:0];

  assign add_signext_82 = sum41;
  assign add_signext_83 = $signed({product43[15:0], 3'b000});
  assign add_temp_41 = add_signext_82 + add_signext_83;
  assign sum42 = (add_temp_41[20] == 1'b0 & add_temp_41[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_41[20] == 1'b1 && add_temp_41[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_41[19:0];

  assign add_signext_84 = sum42;
  assign add_signext_85 = $signed({product44[15:0], 3'b000});
  assign add_temp_42 = add_signext_84 + add_signext_85;
  assign sum43 = (add_temp_42[20] == 1'b0 & add_temp_42[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_42[20] == 1'b1 && add_temp_42[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_42[19:0];

  assign add_signext_86 = sum43;
  assign add_signext_87 = $signed({product45[15:0], 3'b000});
  assign add_temp_43 = add_signext_86 + add_signext_87;
  assign sum44 = (add_temp_43[20] == 1'b0 & add_temp_43[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_43[20] == 1'b1 && add_temp_43[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_43[19:0];

  assign add_signext_88 = sum44;
  assign add_signext_89 = $signed({product46[15:0], 3'b000});
  assign add_temp_44 = add_signext_88 + add_signext_89;
  assign sum45 = (add_temp_44[20] == 1'b0 & add_temp_44[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_44[20] == 1'b1 && add_temp_44[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_44[19:0];

  assign add_signext_90 = sum45;
  assign add_signext_91 = $signed({product47[15:0], 3'b000});
  assign add_temp_45 = add_signext_90 + add_signext_91;
  assign sum46 = (add_temp_45[20] == 1'b0 & add_temp_45[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_45[20] == 1'b1 && add_temp_45[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_45[19:0];

  assign add_signext_92 = sum46;
  assign add_signext_93 = $signed({product48[15:0], 3'b000});
  assign add_temp_46 = add_signext_92 + add_signext_93;
  assign sum47 = (add_temp_46[20] == 1'b0 & add_temp_46[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_46[20] == 1'b1 && add_temp_46[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_46[19:0];

  assign add_signext_94 = sum47;
  assign add_signext_95 = $signed({product49[15:0], 3'b000});
  assign add_temp_47 = add_signext_94 + add_signext_95;
  assign sum48 = (add_temp_47[20] == 1'b0 & add_temp_47[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_47[20] == 1'b1 && add_temp_47[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_47[19:0];

  assign add_signext_96 = sum48;
  assign add_signext_97 = $signed({product50[15:0], 3'b000});
  assign add_temp_48 = add_signext_96 + add_signext_97;
  assign sum49 = (add_temp_48[20] == 1'b0 & add_temp_48[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_48[20] == 1'b1 && add_temp_48[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_48[19:0];

  assign add_signext_98 = sum49;
  assign add_signext_99 = $signed({product51[15:0], 3'b000});
  assign add_temp_49 = add_signext_98 + add_signext_99;
  assign sum50 = (add_temp_49[20] == 1'b0 & add_temp_49[19] != 1'b0) ? 20'b01111111111111111111 : 
      (add_temp_49[20] == 1'b1 && add_temp_49[19] != 1'b1) ? 20'b10000000000000000000 : add_temp_49[19:0];

  assign output_typeconvert = (sum50[19] == 1'b0 & sum50[18:0] != 19'b0000000000000000000) ? 8'b01111111 : 
      (sum50[19] == 1'b1 && sum50[18:0] != 19'b1111111111111111111) ? 8'b10000000 : $signed({sum50[19], 7'b0000000});

  always @ (posedge clk or posedge reset)
    begin: Output_Register_process
      if (reset == 1'b1) begin
        output_register <= 0;
      end
      else begin
        if (clk_enable == 1'b1) begin
          output_register <= output_typeconvert;
        end
      end
    end // Output_Register_process

  // Assignment Statements
  assign data_out = output_register;
endmodule  // basicfir