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Abhirecket/README.md

Hi 👋, I'm Abhishek Kumar Kushwaha

A passionate RTL Design Engineer from India

  • 🔭 I’m currently working on Processor design

  • 🌱 I’m currently learning RISC-V

  • 👯 I’m looking to collaborate on RISC-V Branch predictor

  • 🤝 I’m looking for help with PS - PL data transfer

  • 👨‍💻 All of my projects are available at Git

  • 📝 I regularly write articles on collegeofvlsi WIP

  • 📫 How to reach me abhirecket0001@gmail.com

  • 📄 Know about my experiences Linkedin

FOR VIVADO PROJECTS:-

First clone the respective project and follow the below path for rtl and tb.

RTL PATH:-

[project_name.src/source_1/new/project_name.v] Ex. for programmable_sequence_detector rtl file location is:-"programmable_sequence_detector/programmable_sequence_detector.srcs/sources_1/new/programmable_sequence_detector.v"

TB PATH:-

[project_name.src/sim_1/new/project_name_tb.v] Ex. for programmable_sequence_detector tb file location is:-"programmable_sequence_detector/programmable_sequence_detector.srcs/sim_1/new/programmable_sequence_detector_tb.v"

Languages and Tools:

VERILOG, SV, CHISEL, SCALA, PYTHON

arduino git linux opencv pandas python pytorch

Pinned

  1. Square-Shape-Detector Square-Shape-Detector Public

    x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.

    Verilog 1

  2. Restoring-Division Restoring-Division Public

    Restoring division for unsigned integer.

    Verilog 1

  3. Programmable-Sequence-Detector2 Programmable-Sequence-Detector2 Public

    Added extra signal to control sequence from user end with load functionality. Please refer Programmable Sequence Detector first.

    Verilog 1

  4. read_comments_as_HDL read_comments_as_HDL Public

    using "AND" gate logic to test "read_comments_as_HDL" synthesis directive

    Verilog 1

  5. BCD BCD Public

    BCD circuit with a minimum logic.

    Verilog 1

  6. frequency-divider--2f-3- frequency-divider--2f-3- Public

    Design the Digital Circuit which gives fout = (2/3) fin.

    Verilog 1