Update refdesigns

tests/refdesigns/aws_f1/1activator_125.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-09259c605b16df7fb",
+    "FpgaImageGlobalId": "agfi-0faf0e3531f0a6dc9"
+}

tests/refdesigns/aws_f1/2activator_125.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-06fc8ba0029452b5c",
+    "FpgaImageGlobalId": "agfi-01df1330a9a038df5"
+}

tests/refdesigns/aws_f1/2activator_15_125.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-0c52d661aacb5dd87",
+    "FpgaImageGlobalId": "agfi-0ebeb11121501c204"
+}

tests/refdesigns/aws_f1/2activator_250_75_swap_activator.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-071708dc76f8061ac",
+    "FpgaImageGlobalId": "agfi-0957864a7d58e235c"
+}

tests/refdesigns/aws_f1/2activator_vhdl_125.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-03b527fb67a79e2df",
+    "FpgaImageGlobalId": "agfi-0ec2ac648033a27df"
+}

tests/refdesigns/aws_f1/2activator_vhdl_15_225.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-06b2b0fb19197b51b",
+    "FpgaImageGlobalId": "agfi-07691b0bba2418a3e"
+}

tests/refdesigns/aws_f1/v7.0.0.0.json

@@ -0,0 +1,4 @@
+{
+    "FpgaImageId": "afi-0c52d661aacb5dd87",
+    "FpgaImageGlobalId": "agfi-0ebeb11121501c204"
+}

tests/test_awsf1_refdesign.py

@@ -115,80 +115,93 @@ def run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_ha
 
 
 @pytest.mark.awsf1
-def test_1activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_1activator_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: 1 single clock kernels with Verilog source
     """
     # Run test
-    design_name = '1activator_axi4_125'
+    design_name = '1activator_125'
     axiclk_freq_ref = 125
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.awsf1
-def test_2activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_2activator_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: single clock kernels with Verilog source
     """
     # Run test
-    design_name = '2activator_axi4_125'
+    design_name = '2activator_125'
     axiclk_freq_ref = 125
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.awsf1
-def test_2activator_axi4_250_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_2activator_15_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: dual clock kernels with Verilog source
     """
     # Run test
-    design_name = '2activator_axi4_250_125'
-    axiclk_freq_ref = 250
+    design_name = '2activator_15_125'
+    axiclk_freq_ref = 15
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.awsf1
-def test_2activator_axi4_vhdl_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_2activator_vhdl_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: single clock kernels with VHDL source
     """
     # Run test
-    design_name = '2activator_axi4_vhdl_125'
+    design_name = '2activator_vhdl_125'
     axiclk_freq_ref = 125
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.awsf1
-def test_2activator_axi4_swap_activator_250_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_2activator_vhdl_15_225(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+    """
+    Test a RTL vivado configuration: dual clock kernels with VHDL source
+    """
+    # Run test
+    design_name = '2activator_vhdl_15_225'
+    axiclk_freq_ref = 15
+    drmclk_freq_ref = 225
+    log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
+                                    log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
+
+
+@pytest.mark.awsf1
+def test_2activator_250_75_swap_activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: dual clock kernels with activators inverted on LGDN bus
     """
     # Run test
-    design_name = '2activator_axi4_swap_activator_250_125'
+    design_name = '2activator_250_75_swap_activator'
     axiclk_freq_ref = 250
-    drmclk_freq_ref = 125
+    drmclk_freq_ref = 75
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.skip(reason='To be manually executed: only used to check the behavior of the DRM Controller IP when 1 activator is missing out of 2')
 @pytest.mark.awsf1
-def test_2activator_2clk_missing_1activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_2activator_missing_1activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a RTL vivado configuration: dual clock kernels with one missing activator
     Verify that is works as expected
     """
     # Run test
-    design_name = '2activator_2clk_missing_1activator'
-    axiclk_freq_ref = 250
+    design_name = '2activator_missing_1activator'
+    axiclk_freq_ref = 15
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)

tests/test_vitis_refdesign.py

@@ -121,8 +121,8 @@ def test_vitis_1activator_200_125(accelize_drm, conf_json, cred_json, async_hand
     Test a vitis configuration: 1 activator with dual clock kernels (AXI clock > DRM clock)
     """
     design_name = 'vitis_1activator_200_125'
-    axiclk_freq_ref = 200
-    drmclk_freq_ref = 125
+    axiclk_freq_ref = 225
+    drmclk_freq_ref = 90
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
@@ -146,8 +146,8 @@ def test_vitis_2activator_vhdl_250_125(accelize_drm, conf_json, cred_json, async
     """
     # Run test
     design_name = 'vitis_2activator_vhdl_250_125'
-    axiclk_freq_ref = 250
-    drmclk_freq_ref = 125
+    axiclk_freq_ref = 225
+    drmclk_freq_ref = 90
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
@@ -172,7 +172,7 @@ def test_vitis_2activator_100_125(accelize_drm, conf_json, cred_json, async_hand
     """
     # Run test
     design_name = 'vitis_2activator_100_125'
-    axiclk_freq_ref = 100
+    axiclk_freq_ref = 90
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
@@ -185,8 +185,8 @@ def test_vitis_2activator_slr_200_125(accelize_drm, conf_json, cred_json, async_
     """
     # Run test
     design_name = 'vitis_2activator_slr_200_125'
-    axiclk_freq_ref = 200
-    drmclk_freq_ref = 125
+    axiclk_freq_ref = 225
+    drmclk_freq_ref = 90
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
@@ -212,20 +212,20 @@ def test_vitis_2activator_dualclkfifo(accelize_drm, conf_json, cred_json, async_
     """
     # Run test
     design_name = 'vitis_2activator_dualclkfifo'
-    axiclk_freq_ref = 200
-    drmclk_freq_ref = 125
+    axiclk_freq_ref = 225
+    drmclk_freq_ref = 90
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)
 
 
 @pytest.mark.skip(reason='No design yet available with 5 activators on high density')
 @pytest.mark.awsxrt
-def test_vitis_5activator_high_density(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_vitis_5activator_high_density_100_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a vitis configuration: 5 dual clock activators in a high density design
     """
     # Run test
-    design_name = 'vitis_5activator_high_density'
+    design_name = 'vitis_5activator_high_density_100_125'
     axiclk_freq_ref = 100
     drmclk_freq_ref = 125
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
@@ -234,14 +234,14 @@ def test_vitis_5activator_high_density(accelize_drm, conf_json, cred_json, async
 
 @pytest.mark.skip(reason='No design yet available with 30 activators')
 @pytest.mark.awsxrt
-def test_vitis_30activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
+def test_vitis_30activator_100_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory):
     """
     Test a vitis configuration: 30 activators
     """
     # Run test
-    design_name = 'vitis_30activator'
-    axiclk_freq_ref = 100
-    drmclk_freq_ref = 125
+    design_name = 'vitis_30activator_100_125'
+    axiclk_freq_ref = 90
+    drmclk_freq_ref = 225
     log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler,
                                     log_file_factory, axiclk_freq_ref, drmclk_freq_ref)