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Rename global_mem_cache_type::write_only
to read_write
#875
Rename global_mem_cache_type::write_only
to read_write
#875
Conversation
@@ -164,7 +164,7 @@ bool cuda_hardware_context::has(device_support_aspect aspect) const { | |||
case device_support_aspect::global_mem_cache_read_only: | |||
return false; | |||
break; | |||
case device_support_aspect::global_mem_cache_write_only: | |||
case device_support_aspect::global_mem_cache_read_write: | |||
return false; |
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Now that the semantics has changed from write-only to read-write - I suspect we will have to return true for CUDA, since I think CUDA hardware has read-write cache. But better check to be sure ;)
@@ -171,7 +171,7 @@ bool hip_hardware_context::has(device_support_aspect aspect) const { | |||
case device_support_aspect::global_mem_cache_read_only: | |||
return false; | |||
break; | |||
case device_support_aspect::global_mem_cache_write_only: | |||
case device_support_aspect::global_mem_cache_read_write: |
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Same question here ;)
@@ -83,7 +83,7 @@ bool omp_hardware_context::has(device_support_aspect aspect) const { | |||
case device_support_aspect::global_mem_cache_read_only: | |||
return false; | |||
break; | |||
case device_support_aspect::global_mem_cache_write_only: | |||
case device_support_aspect::global_mem_cache_read_write: |
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CPUs definitely have read-write cache
@@ -263,7 +263,7 @@ bool ze_hardware_context::has(device_support_aspect aspect) const { | |||
case device_support_aspect::global_mem_cache_read_only: | |||
return false; | |||
break; | |||
case device_support_aspect::global_mem_cache_write_only: | |||
case device_support_aspect::global_mem_cache_read_write: |
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Same question here
case device_support_aspect::global_mem_cache_write_only: | ||
return false; | ||
case device_support_aspect::global_mem_cache_read_write: | ||
return true; |
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I couldn't actually find a reference stating that all devices that can be used with Level Zero have read/write cache but dpc++ returns true here, and I think we can trust that this is true then.
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Agreed :)
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From my side this looks good. Is this ready to go @nilsfriess ?
Yes it is :) |
According to Table 25 in section A.3 of the SYCL 2020 Specification, the enum
global_mem_cache_type
should contain the entriesnone
,read_only
, andread_write
. The last one was calledwrite_only
in hipSYCL, this PR renames it (and also other "linked" names to be consistent with naming).Should fix #432