VerilogProcessor

Processor schematic

Tools

use Instruction Encoder to create binary instructions and ModelSim for simulations

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
.qsys_edit		.qsys_edit
db		db
img		img
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
work		work
.gitignore		.gitignore
IRn.v		IRn.v
IRn.v.bak		IRn.v.bak
Processor.cr.mti		Processor.cr.mti
Processor.mpf		Processor.mpf
Programa1.txt		Programa1.txt
README.md		README.md
addsub.v		addsub.v
addsub.v.bak		addsub.v.bak
dec3to8.v		dec3to8.v
dec3to8.v.bak		dec3to8.v.bak
hexto7segment.v		hexto7segment.v
ld.PNG		ld.PNG
loop.PNG		loop.PNG
main.v.bak		main.v.bak
mem.v.bak		mem.v.bak
modelsim.ini		modelsim.ini
mux.v		mux.v
mux.v.bak		mux.v.bak
proc.v		proc.v
proc.v.bak		proc.v.bak
processor.qpf		processor.qpf
processor.qsf		processor.qsf
processor.qws		processor.qws
processor.v		processor.v
processor.v.bak		processor.v.bak
prog1wave.PNG		prog1wave.PNG
regn.v		regn.v
regn.v.bak		regn.v.bak
sd.PNG		sd.PNG
sll.png		sll.png
slt.png		slt.png
srl.png		srl.png
tabelaInstrucoes.txt		tabelaInstrucoes.txt
upcount.v		upcount.v
upcount.v.bak		upcount.v.bak
vsim.wlf		vsim.wlf
wlft0txev9		wlft0txev9
wlft1ykkfx		wlft1ykkfx
wlft5dta1s		wlft5dta1s
wlft5zbmj3		wlft5zbmj3
wlft70m4dx		wlft70m4dx
wlft73je9g		wlft73je9g
wlfta63ykq		wlfta63ykq
wlftbq097y		wlftbq097y
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wlftgt7mv1		wlftgt7mv1
wlfthme37j		wlfthme37j
wlftifrcem		wlftifrcem
wlftm0i7vi		wlftm0i7vi
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wlftsxnk02		wlftsxnk02
wlftv0rqnk		wlftv0rqnk
wlftv2nvvc		wlftv2nvvc
wlftvf9ewk		wlftvf9ewk
wlftvyib6x		wlftvyib6x
wlftwdt4r2		wlftwdt4r2
wlftwh0ya2		wlftwh0ya2
wlftwq14x4		wlftwq14x4

Agronault/VerilogProcessor

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