GitHub - Akhil-Yada/Adaptive-Filter: An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the Delayed Least Mean Squared Algorithm. Concepts of VLSI and Digital Design such as Carry Save Addition, Fixed Point Arithmetic, Offset Binary Coding, Distributed Arithmetic and Low power optimization techniques were incorporated. Three models were proposed which excel in particular aspects such as throughput, delay, area and power. Better throughput was achieved compared to an existing design for an Order-4 Filter. The architecture required to store the pre computed values of weight combinations in a Look Up Table was greatly reduced due to the implementation of Offset Binary Coding. Proposed design was coded and verified in Verilog HDL.

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An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the Delayed Least Mean Squared Algorithm. Concepts of VLSI and Digital Design such as Carry Save Addition, Fixed Point Arithmetic, Offset Binary Coding, Distributed Arithmetic and Low power optimization techniques…

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
10FA.v		10FA.v
10_bit_add.v		10_bit_add.v
10_bit_addsub.v		10_bit_addsub.v
10_bit_sub.v		10_bit_sub.v
12FA.v		12FA.v
13FA.v		13FA.v
Adder_Block.v		Adder_Block.v
Adder_Block15.v		Adder_Block15.v
Barrel_Shifter.v		Barrel_Shifter.v
Barrel_Shifter_Base.v		Barrel_Shifter_Base.v
Barrel_Shifter_Block15.v		Barrel_Shifter_Block15.v
Barrel_Shifter_c.v		Barrel_Shifter_c.v
Base_Paper.cr.mti		Base_Paper.cr.mti
Base_Paper.mpf		Base_Paper.mpf
CSA_Block.v		CSA_Block.v
CSA_unit.v		CSA_unit.v
CSA_unit2.v		CSA_unit2.v
ControlWord_SignMagnitude.v		ControlWord_SignMagnitude.v
DA.v		DA.v
DA1.v		DA1.v
DA11.v		DA11.v
DA2.v		DA2.v
DA3.v		DA3.v
D_flip_flop.v		D_flip_flop.v
D_flip_flop_pre.v		D_flip_flop_pre.v
Design_1.v		Design_1.v
Design_2.v		Design_2.v
Design_3.v		Design_3.v
Designf1.cr.mti		Designf1.cr.mti
Designf1.mpf		Designf1.mpf
Designf2.cr.mti		Designf2.cr.mti
Designf2.mpf		Designf2.mpf
FilterX.v		FilterX.v
FilterX2.v		FilterX2.v
FilterX3.v		FilterX3.v
FilterXb.v		FilterXb.v
FilterXm.v		FilterXm.v
Full_Adder.v		Full_Adder.v
Half_Adder.v		Half_Adder.v
Input_Table.v		Input_Table.v
MUX16_1.v		MUX16_1.v
MUX2_1.v		MUX2_1.v
MUX8_1.v		MUX8_1.v
MUX8_18.v		MUX8_18.v
Modified_Adder_Block.v		Modified_Adder_Block.v
Order8.cr.mti		Order8.cr.mti
Order8.mpf		Order8.mpf
Output_Error1.v		Output_Error1.v
Output_Error3.v		Output_Error3.v
Output_Error_Block.v		Output_Error_Block.v
Register_Table.v		Register_Table.v
Register_Table15.v		Register_Table15.v
T_flip_flop.v		T_flip_flop.v
T_flip_flop_pre.v		T_flip_flop_pre.v
barrel_shifter_block.v		barrel_shifter_block.v
carry_computator.v		carry_computator.v
controller1.v		controller1.v
counter8.v		counter8.v
input_reg_table.v		input_reg_table.v
input_table_b.v		input_table_b.v
input_table_m.v		input_table_m.v
modelsim.ini		modelsim.ini
modified_adder_unit.v		modified_adder_unit.v
test.cr.mti		test.cr.mti
test.mpf		test.mpf
test_controller.v		test_controller.v
testbenchaddertree.v		testbenchaddertree.v