A permutations enumerator circuit based on Lehmer's code; synthesis and verification frameworks are provided.
LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license.
Please refer to the full paper for more information:
A. Abdelhadi and G. Lemieux, "Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations," Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig '11), pp. 20-26, Dec. 2011. http://ece.ubc.ca/~ameer/publications/Abdelhadi-Conference-2011Dec-ReConfig2011-BitstreamReduction.pdf