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1. AES-128-decryption-using-Verilog AES-128-decryption-using-Verilog Public

   designing hardware using Verilog to decrypt AES message and implement the design with less than 3% of zynq FPGA resources in one-lab CU competition

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2. Digital-Design-Recap Digital-Design-Recap Public

   A simple Recap for different Digital Design topics from different references and books.

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