SRAM is a memory component and is used in various VLSI chips due to its unique capability to retain data. This memory cell has become a subject of research to meet the demands for future communication systems. In this paper a 6T SRAM cell is designed by using Verilog and esim software. Static random-access memory (SRAM) is a static memory cell which is widely used in various electronic systems. It is faster and consumes less power as compared to other memory cells [1-2]. It does not require refreshing periodically. Because of this, SRAM is the most popular memory cell among VLSI designers.
Hence continuous evolution is going on for better performance of SRAM cells. Due to this, different types of SRAM cells are available in the literature like 6T SRAM cell, 7T SRAM cell, 8T SRAM cell, 9T SRAM cell etc. Most common SRAM cells used in digital system is the 6T SRAM cell. This cell can store 1- bit of data. The bit remains in the cell as long as power is supplied. A conventional 6T SRAM cell consists of two inverters which are connected back-to-back. Fig. 1 shows the basic structure of a 6T SRAM memory cell [1]. The data which must be stored is latched in these two inverters. The process of storing a data is known as Write operation and the process of recovering the data is known as Read operation. Write operation is used for uploading the contents in a SRAM cell while Read operation is used for fetching the contents. The read operation is done with the help of sense circuits which sense BL and BLB data line before discharging it completely Basically, SRAM performs three operations which are Hold, Read and Write operations. ... Whenever the two access pass transistors of the word line (WL) are in OFF state, then the bit line and bit line bar (BL & BLB) are also in OFF condition, hence the memory cell is in hold state .
eSim It is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD. For more details refer: https://esim.fossee.in/home
NgSpice It is an Open Source Software for Spice Simulations. For more details refer: http://ngspice.sourceforge.net/docs.html
Makerchip It is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. Refer https://www.makerchip.com/ Verilator It is a tool which converts Verilog code to C++ objects. Refer: https://www.veripool.org/verilator/
The following is the schematic in eSim:
\TLV_version 1d: tl-x.org
\SV
/* verilator lint_off UNUSED*/ /* verilator lint_off DECLFILENAME*/ /* verilator lint_off BLKSEQ*/ /* verilator lint_off WIDTH*/ /* verilator lint_off SELRANGE*/ /* verilator lint_off PINCONNECTEMPTY*/ /* verilator lint_off DEFPARAM*/ /* verilator lint_off IMPLICIT*/ /* verilator lint_off COMBDLY*/ /* verilator lint_off SYNCASYNCNET*/ /* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNSIGNED*/ /* verilator lint_off CASEINCOMPLETE*/ /* verilator lint_off UNDRIVEN*/ /* verilator lint_off VARHIDDEN*/ /* verilator lint_off CASEX*/ /* verilator lint_off CASEOVERLAP*/ /* verilator lint_off PINMISSING*/ /* verilator lint_off BLKANDNBLK*/ /* verilator lint_off MULTIDRIVEN*/ /* verilator lint_off WIDTHCONCAT*/ /* verilator lint_off ASSIGNDLY*/ /* verilator lint_off MODDUP*/ /* verilator lint_off STMTDLY*/ /* verilator lint_off LITENDIAN*/ /* verilator lint_off INITIALDLY*/
//Your Verilog/System Verilog Code Starts Here:
module ixorxnor(output yXOR,output yXNOR, input a,input b);
assign yXOR = a ^ b;
assign yXNOR = ~(a ^ b);
endmodule
//Top Module Code Starts here:
module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);
logic yXOR;//output
logic yXNOR;//output
logic a;//input
logic b;//input
//The $random() can be replaced if user wants to assign values'
always @(posedge clk)
begin
a = $random();
b = $random();
end
ixorxnor ixorxnor(.yXOR(yXOR), .yXNOR(yXNOR), .a(a), .b(b));
\TLV
//Add \TLV here if desired
\SV
endmodule
1.Open a new terminal.
2.Clone this project using the following command: git clone https://github.com/AnkitKumar01github/6T-SRAM-IN-CMOS.git
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Change directory: cd eSim_project_files/6T-SRAM-IN-CMOS
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Run ngspice: ngspice 6T-SRAM-IN-CMOS.cir.out
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To run the project in eSim: Run eSim, Load the project, Open eeSchema
1.Rohit Kumar Sah1 , Inamul Hussain 2 , Manish Kumar3 1,2,3 Department of ECE, North-eastern Regional Institute of Science & Technology, Nirjuli, India, https://www.iosrjournals.org/iosr-jvlsi/papers/vol5-issue2/Version-1/C05212022.pdf