Graduate student at Purdue Univ (ECE) majoring in VLSI circuit design. Interests: Computer architecture, RTL design and modeling
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AHB-MUX-Verif
AHB-MUX-Verif PublicUVM verification of manager selection multiplexor of AHB-Lite protocol
SystemVerilog 1
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MatrixMultiplication
MatrixMultiplication PublicA matrix multiplication module for multiplying two complex valued square matrices
SystemVerilog
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