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This electronic circuit is intended to generate discrete signal pulses from an avionic ARINC 429 digital bus without using any microcontroller. The bare PCB can be ordered to OSHPark.
The circuit generates a 1ms negative pulse at each occurrence of the octal label 377 (all bits to one). It can also be used to detect label 000 just by swapping H an L input lines.
The board surface is 4 squared-inches (2.8” x 1.4”). It is made of old-fashioned through-hole components like CD4093 Schmitt trigger NAND gates and of an NE555 timer:
The operation is based on various Schmitt trigger CMOS gates, on delays and on flip-flops.
A first stage is made of two Schmitt trigger inverters (IC1A and IC1B) connected to the H and L lines of the ARINC bus through 22k resistors. The bus signals are swinging between -5V and +5V while the Schmitt trigger inverter gates are supplied between +5V and ground. But the ESD protection diodes at the input of the CD4093 gates associated with the 22k resistors eliminate the negative alternances. The IC1A gate outputs the ones, and the IC1B one outputs the zeroes. Such an ARINC429 receiver is not very performant since its architecture is not differential. In presence of significant common mode voltage (>2.5V), the input would be saturated and the ARINC signal would not be read anymore. It has proved to work well however in regular situations.
A second stage makes a logical OR between the ones and the zeroes to generate the bit clock. The OR function is implemented with a NAND gate. This is based on the complemented inputs and on the De Morgan's law:
NOT (NOT Ones AND NOT Zeroes) = Ones OR Zeroes
The following plot is the result of a simulation test. The test vector is an ARINC frame of two words. The first one is an alternance of ones and zeroes. The gap between the two words is compliant with the standard (4 bit periods). The second word has the label 377 to be detected.
One can observe that the first signal (VM1) goes low at each occurence of a "one" bit on the bus. VM2 is low for zero's. And VM3 is the bit clock. It exhibits 32 pulses per word as expected:
The following plot uses the same test vector. The monitored signals are the bit clock, the voltage across the word gap detector capacitor; and the word clock. The effect of the diode can be noticed: the time constant is longer when the voltage decreases across the capacitor than when it increases:
A timer is used to generate negative pulses starting at the begining of each ARINC word, with a duration of 8 bit exactly.
Note: this timer can be tuned for different durations. For instance, with a duration of 10 bits, the detector will only trigger on occurrence of labels 377 having an SDI=11.
These pulses constitute the markers of the label phases. The timer is built from an NE555 rather than from NAND gates. This is to guarantee the accuracy of the pulse duration. The capacitor was also selected of NP0 ceramic type to ensure temperature stability:
The core of the label detection is based on an SR (Set/Reset) flip-flop (signal VM2).
This flip-flop is set on the falling edge (i.e. at the begining) of the label mask pulse (VM1).
It is reset upon the occurence of any zero in the ARINC word (VM3).
At the end of the label mask pulse (rising edge) a pulse is generated (VM4) if the flip-flop is still high.
Hence this VM4 pulse only occurs if all of the first 8 bits of an ARINC word are ones:
An output negatve pulse of 1ms is desired. This is achieved with a monostable. Since accuracy is not an issue, NAND gates are used:
