pcie: Set link speed capabilities from ADT

This sets both the target and the max link speed of the root ports to the maximum specified in the ADT. Signed-off-by: Hector Martin <marcan@marcan.st>
AsahiLinux · Dec 7, 2021 · abee2ec · abee2ec
1 parent c9dc440
commit abee2ec
Showing 1 changed file with 30 additions and 1 deletion.
diff --git a/src/pcie.c b/src/pcie.c
@@ -58,6 +58,15 @@
 #define APCIE_PORT_RESET     0x814
 #define APCIE_PORT_RESET_DIS BIT(0)
 
+/* PCIe capability registers */
+#define PCIE_CAP_BASE    0x70
+#define PCIE_LNKCAP      0x0c
+#define PCIE_LNKCAP_SLS  GENMASK(3, 0)
+#define PCIE_LNKCAP2     0x2c
+#define PCIE_LNKCAP2_SLS GENMASK(6, 1)
+#define PCIE_LNKCTL2     0x30
+#define PCIE_LNKCTL2_TLS GENMASK(3, 0)
+
 /* DesignWare PCIe Core registers */
 
 #define DWC_DBI_RO_WR    0x8bc
@@ -240,14 +249,15 @@ int pcie_init(void)
 
     for (u32 port = 0; port < port_count; port++) {
         char bridge[64];
+        int bridge_offset;
 
         /*
          * Initialize RC port.
          */
 
         snprintf(bridge, sizeof(bridge), "/arm-io/apcie/pci-bridge%d", port);
 
-        if (adt_path_offset(adt, bridge) < 0)
+        if ((bridge_offset = adt_path_offset(adt, bridge)) < 0)
             continue;
 
         printf("pcie: Initializing port %d\n", port);
@@ -296,6 +306,25 @@ int pcie_init(void)
             return -1;
         }
 
+        u32 max_speed;
+        if (ADT_GETPROP(adt, bridge_offset, "maximum-link-speed", &max_speed) >= 0) {
+            printf("pcie: Port %d max speed = %d\n", port, max_speed);
+
+            if (max_speed == 0) {
+                printf("pcie: Invalid max-speed\n");
+                return -1;
+            }
+
+            mask32(config_base + PCIE_CAP_BASE + PCIE_LNKCAP, PCIE_LNKCAP_SLS,
+                   FIELD_PREP(PCIE_LNKCAP_SLS, max_speed));
+
+            mask32(config_base + PCIE_CAP_BASE + PCIE_LNKCAP2, PCIE_LNKCAP2_SLS,
+                   FIELD_PREP(PCIE_LNKCAP2_SLS, (1 << max_speed) - 1));
+
+            mask16(config_base + PCIE_CAP_BASE + PCIE_LNKCTL2, PCIE_LNKCTL2_TLS,
+                   FIELD_PREP(PCIE_LNKCTL2_TLS, max_speed));
+        }
+
         set32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_SPEED_CHANGE);
 
         /* Make Designware PCIe Core registers readonly. */