This is my Lab assignments for the course Computer Architecture, Zhejiang University. My course tutor is Jiang Xiaohong.
Finally we finish a pipeline CPU supporting stall, forwarding, predit-not-taken and interrupt.
Extend single-cycle CPU(in Org) to run on Sword V4.
5-stage pipelined CPU with 23 MIPS instructions.
Execute program in pipeline correctly implementing "stall" when have hazards, using flushing approach to solve control hazard.
Implement forwarding paths and predict-not-taken to make CPU run faster.
Design of Pipelined CPU supporting Interrupt, adding co-processor CP0.
Warning: VGA-debug has strange bugs(jump doesn't work), but simulation is correct.
