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| Original file line number | Diff line number | Diff line change |
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| # sept | ||
| Sept is a payload that facilitates booting Atmosphère when targeting firmware version 7.0.0+. | ||
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| It consists of a primary and a secondary payload. | ||
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| ## Sept-Primary | ||
| Sept-primary is essentially a stand-in for Nintendo's package1ldr, on 7.0.0+. To use it, the caller (normally Fusée-secondary) loads the sept-primary binary to `0x4003F000`, | ||
| loads the 7.0.0+ TSEC firmware to `0x40010F00`, and loads a signed, encrypted payload to `0x40016FE0`. | ||
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| This signed, encrypted payload is normally Sept-secondary. | ||
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| ## Sept-Secondary | ||
| Sept-secondary is a payload that performs 7.0.0+ key derivation, and then chainloads to `sept/payload.bin`. | ||
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| It is normally stored encrypted/signed; if one wishes to build sept-secondary instead of using release builds, one must bring his/her own keys. |
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| /* | ||
| * Copyright (c) 2018 Atmosphère-NX | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify it | ||
| * under the terms and conditions of the GNU General Public License, | ||
| * version 2, as published by the Free Software Foundation. | ||
| * | ||
| * This program is distributed in the hope it will be useful, but WITHOUT | ||
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| * more details. | ||
| * | ||
| * You should have received a copy of the GNU General Public License | ||
| * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| */ | ||
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| #include "max77620.h" | ||
| #include "i2c.h" | ||
| #include "timer.h" | ||
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| /* Prototypes for internal commands. */ | ||
| void i2c_load_config(void); | ||
| int i2c_write(unsigned int device, uint32_t val, unsigned int num_bytes); | ||
| int i2c_read(unsigned int device, void *dst, unsigned num_bytes); | ||
| int i2c_query(uint8_t device, uint8_t r, void *dst, size_t num_bytes); | ||
| int i2c_send_byte_command(unsigned int device, unsigned char reg, unsigned char b); | ||
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| /* Load hardware config for I2C4. */ | ||
| void i2c_load_config(void) { | ||
| /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */ | ||
| I2C_I2C_CONFIG_LOAD_0 = 0x25; | ||
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| /* Wait a bit for master config to be loaded. */ | ||
| for (unsigned int i = 0; i < 20; i++) { | ||
| timer_wait(1); | ||
| if (!(I2C_I2C_CONFIG_LOAD_0 & 1)) { | ||
| break; | ||
| } | ||
| } | ||
| } | ||
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| /* Initialize I2C4. */ | ||
| void i2c_init(void) { | ||
| /* Setup divisor, and clear the bus. */ | ||
| I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001; | ||
| I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003; | ||
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| /* Load hardware configuration. */ | ||
| i2c_load_config(); | ||
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| /* Wait a while until BUS_CLEAR_DONE is set. */ | ||
| for (unsigned int i = 0; i < 10; i++) { | ||
| timer_wait(20000); | ||
| if (I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) { | ||
| break; | ||
| } | ||
| } | ||
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| /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */ | ||
| I2C_I2C_BUS_CLEAR_STATUS_0; | ||
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| /* Read and set the Interrupt Status. */ | ||
| uint32_t int_status = I2C_INTERRUPT_STATUS_REGISTER_0; | ||
| I2C_INTERRUPT_STATUS_REGISTER_0 = int_status; | ||
| } | ||
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| /* Writes a value to an i2c device. */ | ||
| int i2c_write(unsigned int device, uint32_t val, unsigned int num_bytes) { | ||
| if (num_bytes > 4) { | ||
| return 0; | ||
| } | ||
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| /* Set device for 7-bit mode. */ | ||
| I2C_I2C_CMD_ADDR0_0 = device << 1; | ||
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| /* Load in data to write. */ | ||
| I2C_I2C_CMD_DATA1_0 = val; | ||
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| /* Set config with LENGTH = num_bytes, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ | ||
| I2C_I2C_CNFG_0 = ((num_bytes << 1) - 2) | 0x2800; | ||
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| i2c_load_config(); | ||
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| /* Config |= SEND; */ | ||
| I2C_I2C_CNFG_0 |= 0x200; | ||
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| while (I2C_I2C_STATUS_0 & 0x100) { | ||
| /* Wait until not busy. */ | ||
| } | ||
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| /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */ | ||
| return (I2C_I2C_STATUS_0 & 0xF) == 0; | ||
| } | ||
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| /* Reads a value from an i2c device. */ | ||
| int i2c_read(unsigned device, void *dst, unsigned num_bytes) { | ||
| if (num_bytes > 4) { | ||
| return 0; | ||
| } | ||
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| /* Set device for 7-bit read mode. */ | ||
| I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1; | ||
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| /* Set config with LENGTH = num_bytes, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ | ||
| I2C_I2C_CNFG_0 = ((num_bytes << 1) - 2) | 0x2840; | ||
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| i2c_load_config(); | ||
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| /* Config |= SEND; */ | ||
| I2C_I2C_CNFG_0 |= 0x200; | ||
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| while (I2C_I2C_STATUS_0 & 0x100) { | ||
| /* Wait until not busy. */ | ||
| } | ||
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| /* Ensure success. */ | ||
| if ((I2C_I2C_STATUS_0 & 0xF) != 0) { | ||
| return 0; | ||
| } | ||
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| uint32_t val = I2C_I2C_CMD_DATA1_0; | ||
| for (size_t i = 0; i < num_bytes; i++) { | ||
| ((uint8_t *)dst)[i] = ((uint8_t *)&val)[i]; | ||
| } | ||
| return 1; | ||
| } | ||
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| /* Queries the value of a register. */ | ||
| int i2c_query(uint8_t device, uint8_t r, void *dst, size_t num_bytes) { | ||
| /* Limit output size to 32-bits. */ | ||
| if (num_bytes > 4) { | ||
| return 0; | ||
| } | ||
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| /* Write single byte register ID to device. */ | ||
| if (!i2c_write(device, r, 1)) { | ||
| return 0; | ||
| } | ||
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| return i2c_read(device, dst, num_bytes); | ||
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| } | ||
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| /* Writes a byte val to reg for given device. */ | ||
| int i2c_send_byte_command(unsigned int device, unsigned char reg, unsigned char b) { | ||
| uint32_t val = (reg) | (b << 8); | ||
| /* Write 1 byte (reg) + 1 byte (value) */ | ||
| return i2c_write(device, val, 2); | ||
| } | ||
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| void i2c_stop_rtc_alarm(void) { | ||
| i2c_send_byte_command(MAX77620_RTC_I2C_ADDR, MAX77620_REG_RTCUPDATE0, 0x10); | ||
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| uint8_t val = 0; | ||
| for (int i = 0; i < 14; i++) { | ||
| if (i2c_query(MAX77620_RTC_I2C_ADDR, 0x0E + i, &val, 1)) { | ||
| val &= 0x7F; | ||
| i2c_send_byte_command(MAX77620_RTC_I2C_ADDR, 0x0E + i, val); | ||
| } | ||
| } | ||
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| i2c_send_byte_command(MAX77620_RTC_I2C_ADDR, MAX77620_REG_RTCUPDATE0, 0x01); | ||
| } | ||
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| void i2c_send_shutdown_cmd(void) { | ||
| i2c_send_byte_command(MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,51 @@ | ||
| /* | ||
| * Copyright (c) 2018 Atmosphère-NX | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify it | ||
| * under the terms and conditions of the GNU General Public License, | ||
| * version 2, as published by the Free Software Foundation. | ||
| * | ||
| * This program is distributed in the hope it will be useful, but WITHOUT | ||
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| * more details. | ||
| * | ||
| * You should have received a copy of the GNU General Public License | ||
| * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| */ | ||
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| #ifndef EXOSPHERE_REBOOTSTUB_I2C_H | ||
| #define EXOSPHERE_REBOOTSTUB_I2C_H | ||
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| #include "utils.h" | ||
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| /* I2C_BASE = I2C4. */ | ||
| #define I2C_BASE (0x7000D000) | ||
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| #define MAKE_I2C_REG(ofs) (MAKE_REG32(I2C_BASE + ofs)) | ||
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| #define I2C_I2C_CNFG_0 MAKE_I2C_REG(0x000) | ||
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| #define I2C_I2C_CMD_ADDR0_0 MAKE_I2C_REG(0x004) | ||
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| #define I2C_I2C_CMD_DATA1_0 MAKE_I2C_REG(0x00C) | ||
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| #define I2C_I2C_STATUS_0 MAKE_I2C_REG(0x01C) | ||
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| #define I2C_INTERRUPT_STATUS_REGISTER_0 MAKE_I2C_REG(0x068) | ||
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| #define I2C_I2C_CLK_DIVISOR_REGISTER_0 MAKE_I2C_REG(0x06C) | ||
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| #define I2C_I2C_BUS_CLEAR_CONFIG_0 MAKE_I2C_REG(0x084) | ||
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| #define I2C_I2C_BUS_CLEAR_STATUS_0 MAKE_I2C_REG(0x088) | ||
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| #define I2C_I2C_CONFIG_LOAD_0 MAKE_I2C_REG(0x08C) | ||
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| void i2c_init(void); | ||
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| void i2c_stop_rtc_alarm(void); | ||
| void i2c_send_shutdown_cmd(void); | ||
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| #endif |
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