GitHub - AymanNasser/Single-Cycle-MIPS-Processor-2019: Developed MIPS Processor Using Verilog HDL, Please Read README.md File for Detailed Description

AymanNasser / Single-Cycle-MIPS-Processor-2019 Public

Developed MIPS Processor Using Verilog HDL, Please Read README.md File for Detailed Description

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
AssemblerPython		AssemblerPython
ALU.v		ALU.v
ALU_Control.v		ALU_Control.v
Basic_Adder.v		Basic_Adder.v
CLOCK_Generation.v		CLOCK_Generation.v
Control_Unit.v		Control_Unit.v
DATA_path.v		DATA_path.v
Data_Memory.v		Data_Memory.v
Instruction_Memory.v		Instruction_Memory.v
Jump_Handler.v		Jump_Handler.v
MUX2to1_13.v		MUX2to1_13.v
MUX2to1_32.v		MUX2to1_32.v
MUX2to1_5.v		MUX2to1_5.v
Program_Counter.v		Program_Counter.v
README.md		README.md
Register_File.v		Register_File.v
Sign_Extension.v		Sign_Extension.v
Test_cases.rar		Test_cases.rar